Stefan Weil wrote: > Thiemo Seufer schrieb: > > Looks very nice, except that the CPU models are out of touch with > > reality. :-) > > - There is no CPU called "R4Kc" etc. > > - What Qemu emulates is currently close to a 4KEc with an R3000-style > > FPU attached. (A 4KEc is a 4Kc with MIPS32R2 instructions.) > There exists also an older 4KEc version which only supports > MIPS32R1. AR7 (a SoC from TI) is based on this older version.
This can't be correct. 4KEc is defined as a MIPS32R2 core by MIPS Technologies. A MIPS32R1 4KEc would be redundant since that's what the 4Kc is. > I noticed this because some code using DI worked well with QEMU, > but my AR7 based DSL router crashed... Did it die with an RI exception? If not then it sounds more like a missing ehb barrier. Qemu doesn't emulate pipeline hazards... > AR7, it would be nice to switch between MIPS32R1 / MIPS32R2 > instruction sets. It would be nice to see a AR7 router emulation as a separate machine type in Qemu. *hint* *hint* :-) > I think this could be done similar to the FPU > switch, but I don't have a list of the differences, and there are > no MIPS32R2 markers in the QEMU code :-( The specificiation for MIPS{32,64}R{1,2} used to be hidden behind a "free registration" nag screen at http://www.mips.com/ . Unfortunately it isn't ATM, it apparently fell through the cracks of the website relaunch. Thiemo _______________________________________________ Qemu-devel mailing list Qemu-devel@nongnu.org http://lists.nongnu.org/mailman/listinfo/qemu-devel