The shift instructions on the SPARC target currently take into account
the whole register as the shift count. According to the SPARC v8 and v9
manuals, only the lower 5 bits should be taken into account for 32-bit
instructions (SLL, SRL, SRA), and only the lower 6 bits for 64-bit
instructions (SLLX, SRLX, SRAX).
The patch below fixes that. Note that SLL and SLLX are now different, as
they don't take into account the same number of bits. Please apply.
Can you check what happens in real hardware, especially in the case when the
shift amount is in a register, not immediate, and the value is either >32 or
==32?
The 64-bit mask should be 0x3f, not 0x2f.
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