Re: [PATCH v3 5/6] target/riscv/tcg: add riscv_cpu_write_misa_bit()

[LIU Zhiwei]

On 2023/10/21 6:39, Daniel Henrique Barboza wrote:

We have two instances of the setting/clearing a MISA bit from
env->misa_ext and env->misa_ext_mask pattern. And the next patch will
end up adding one more.

Create a helper to avoid code repetition.

Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
---
  target/riscv/tcg/tcg-cpu.c | 44 ++++++++++++++++++++------------------
  1 file changed, 23 insertions(+), 21 deletions(-)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 59b75a14ac..ba11d0566d 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -42,6 +42,20 @@ static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset)
                                   GUINT_TO_POINTER(ext_offset));
  }

+static void riscv_cpu_write_misa_bit(RISCVCPU *cpu, uint32_t bit,

+                                     bool enabled)
+{
+    CPURISCVState *env = &cpu->env;
+
+    if (enabled) {
+        env->misa_ext |= bit;
+        env->misa_ext_mask |= bit;
+    } else {
+        env->misa_ext &= ~bit;
+        env->misa_ext_mask &= ~bit;
+    }
+}
+
  static void riscv_cpu_synchronize_from_tb(CPUState *cs,
                                            const TranslationBlock *tb)
  {
@@ -680,20 +694,14 @@ static void cpu_set_misa_ext_cfg(Object *obj, Visitor *v, 
const char *name,
          return;
      }

- if (value) {

-        if (!generic_cpu) {
-            g_autofree char *cpuname = riscv_cpu_get_name(cpu);
-            error_setg(errp, "'%s' CPU does not allow enabling extensions",
-                       cpuname);
-            return;
-        }
-
-        env->misa_ext |= misa_bit;
-        env->misa_ext_mask |= misa_bit;
-    } else {
-        env->misa_ext &= ~misa_bit;
-        env->misa_ext_mask &= ~misa_bit;
+    if (value && !generic_cpu) {
+        g_autofree char *cpuname = riscv_cpu_get_name(cpu);
+        error_setg(errp, "'%s' CPU does not allow enabling extensions",
+                   cpuname);
+        return;
      }
+
+    riscv_cpu_write_misa_bit(cpu, misa_bit, value);
  }

static void cpu_get_misa_ext_cfg(Object *obj, Visitor *v, const char *name,

@@ -737,7 +745,6 @@ static const RISCVCPUMisaExtConfig misa_ext_cfgs[] = {
   */
  static void riscv_cpu_add_misa_properties(Object *cpu_obj)
  {
-    CPURISCVState *env = &RISCV_CPU(cpu_obj)->env;
      bool use_def_vals = riscv_cpu_is_generic(cpu_obj);
      int i;

@@ -758,13 +765,8 @@ static void riscv_cpu_add_misa_properties(Object *cpu_obj)

                              NULL, (void *)misa_cfg);
          object_property_set_description(cpu_obj, name, desc);
          if (use_def_vals) {
-            if (misa_cfg->enabled) {
-                env->misa_ext |= bit;
-                env->misa_ext_mask |= bit;
-            } else {
-                env->misa_ext &= ~bit;
-                env->misa_ext_mask &= ~bit;
-            }
+            riscv_cpu_write_misa_bit(RISCV_CPU(cpu_obj), bit,
+                                     misa_cfg->enabled);

Reviewed-by: LIU Zhiwei <zhiwei_...@linux.alibaba.com>

Zhiwei

          }
      }
  }