On Mon, 6 Nov 2023 15:05:33 +0100 Igor Mammedov (IM) wrote: > it might be worth mentioning that QEMU impl. uses 32 bit registers and > can correctly handle 32 bit access only, while 16 (or any other) bit access > to 32 bit registers won't actually work. > > ex: > pl011_write() > ... > switch (offset >> 2) > > essentially only 1st byte will be accessed correctly, > the rest will be misplaced as read/write handlers do not account > for split access possibility. > > So it's not about what linux or NOVA do, but rather fixing > ACPI description to match what the device model is capable of.
The latest version of Peter's patch series advertises 32-bit access width, so that should not derail the current PL011 device model anymore. Independent of that, the PL011 device model should be fixed to also support 8-bit and 16-bit accesses, because the PL011 data sheet says 16-bit and the SBSA says 8-, 16- and 32-bit accesses are valid, so if the model cannot handle 8 and 16, it is incomplete/buggy. Cheers, Udo
