Hello,
Thank you for the review and suggestions on V5.
The suggestions and changes requested from V5 are addressed in V6.
Updates in Version 6 of this series are:
1. adding a device-tree node in QEMU is removed as skiboot defines the
device-tree and QEMU should just follow it.
2. Renamed PnvPerv to PnvNestChipletPervasive in PATCH1 as the model provides
the common pervasive registers of all nest chiplets.
3. Nest1_chiplet model in PATCH2 is renamed to N1_chiplet to avoid the
confussions that may comeup later.
Hence the new qom-tree looks like below.
(qemu) info qom-tree
/machine (powernv10-machine)
/chip[0] (power10_v2.0-pnv-chip)
/n1_chiplet (pnv-N1-chiplet)
/nest_pervasive_common (pnv-nest-chiplet-pervasive)
/xscom-n1_chiplet-control-regs[0] (memory-region)
/xscom-n1_chiplet-pb-scom-eq-regs[0] (memory-region)
/xscom-n1_chiplet-pb-scom-es-regs[0] (memory-region)
Patches overview in V6.
PATCH1: Create a common nest pervasive chiplet model with control chiplet scom
registers.
PATCH2: Create a N1 chiplet model and implement powerbus scom registers.
Connect common nest pervasive model to N1 chiplet model to define
chiplet control scoms for N1 chiplet.
PATCH3: Connect N1 chiplet model to p10 chip.
Test covered:
These changes are tested on a single socket and 2 socket P10 machine.
Thank You,
Chalapathi
Chalapathi V (3):
hw/ppc: Add pnv nest pervasive common chiplet model
hw/ppc: Add N1 chiplet model
hw/ppc: N1 chiplet wiring
include/hw/ppc/pnv_chip.h | 2 +
include/hw/ppc/pnv_n1_chiplet.h | 35 +++++
include/hw/ppc/pnv_nest_pervasive.h | 36 +++++
include/hw/ppc/pnv_xscom.h | 9 ++
hw/ppc/pnv.c | 15 ++
hw/ppc/pnv_n1_chiplet.c | 171 ++++++++++++++++++++++
hw/ppc/pnv_nest_pervasive.c | 219 ++++++++++++++++++++++++++++
hw/ppc/meson.build | 2 +
8 files changed, 489 insertions(+)
create mode 100644 include/hw/ppc/pnv_n1_chiplet.h
create mode 100644 include/hw/ppc/pnv_nest_pervasive.h
create mode 100644 hw/ppc/pnv_n1_chiplet.c
create mode 100644 hw/ppc/pnv_nest_pervasive.c
--
2.31.1
