Set the properties on the mpcore object to let it create and wire the CPU cores. Remove the redundant code.
Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org> --- hw/arm/xilinx_zynq.c | 22 +++++----------------- 1 file changed, 5 insertions(+), 17 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 28430dcfba..736e2115a6 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -192,22 +192,6 @@ static void zynq_init(MachineState *machine) exit(EXIT_FAILURE); } - cpu = ARM_CPU(object_new(machine->cpu_type)); - - /* By default A9 CPUs have EL3 enabled. This board does not - * currently support EL3 so the CPU EL3 property is disabled before - * realization. - */ - if (object_property_find(OBJECT(cpu), "has_el3")) { - object_property_set_bool(OBJECT(cpu), "has_el3", false, &error_fatal); - } - - object_property_set_int(OBJECT(cpu), "midr", ZYNQ_BOARD_MIDR, - &error_fatal); - object_property_set_int(OBJECT(cpu), "reset-cbar", MPCORE_PERIPHBASE, - &error_fatal); - qdev_realize(DEVICE(cpu), NULL, &error_fatal); - /* DDR remapped to address zero. */ memory_region_add_subregion(address_space_mem, 0, machine->ram); @@ -239,15 +223,19 @@ static void zynq_init(MachineState *machine) sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); dev = qdev_new(TYPE_A9MPCORE_PRIV); - qdev_prop_set_uint32(dev, "num-cpu", 1); + qdev_prop_set_uint32(dev, "num-cores", 1); + qdev_prop_set_string(dev, "cpu-type", machine->cpu_type); /* * By default A9 CPUs have EL3 enabled. This board does not * currently support EL3 so the CPU EL3 property is disabled before * realization. */ qdev_prop_set_bit(dev, "cpu-has-el3", false); + qdev_prop_set_uint64(dev, "cpu-reset-cbar", MPCORE_PERIPHBASE); + qdev_prop_set_uint64(dev, "cpu-midr", ZYNQ_BOARD_MIDR); busdev = SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); + cpu = CORTEX_MPCORE_PRIV(dev)->cpu[0]; sysbus_mmio_map(busdev, 0, MPCORE_PERIPHBASE); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ)); -- 2.41.0