This patch series builds on a discussion initiated by Anton Kochkov on this list in 2022. It allows setting the appropriate number of priority bits for Cortex-M devices. For example, FreeRTOS checks at startup that the right number of priority bits is available in order to guarantee its runtime structures safety. They added a configuration option specially for QEMU to disable this check because QEMU always use 2 bits for Cortex-M0/M0+/M1 and 8 bits for other devices.
While this change allows the number of priority bits to be properly configured, it keeps the same default as before in order to preserve backward compatibility. Based-on: <20220813112559.1974427-1-anton.koch...@proton.me> ([PATCH] hw/arm/nvic: implement "num-prio-bits" property) Samuel Tardieu (3): hw/intc/armv7m_nvic: add "num-prio-bits" property hw/arm/armv7m: alias the NVIC "num-prio-bits" property hw/arm/socs: configure priority bits for existing SOCs hw/arm/armv7m.c | 2 ++ hw/arm/stellaris.c | 2 ++ hw/arm/stm32f100_soc.c | 1 + hw/arm/stm32f205_soc.c | 1 + hw/arm/stm32f405_soc.c | 1 + hw/intc/armv7m_nvic.c | 23 ++++++++++++++++++++++- 6 files changed, 29 insertions(+), 1 deletion(-) -- 2.42.0
