On Mon, Dec 18, 2023 at 10:54 PM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > zic64b is defined in the RVA22U64 profile [1] as a named feature for > "Cache blocks must be 64 bytes in size, naturally aligned in the address > space". It's a fantasy name for 64 bytes cache blocks. The RVA22U64 > profile mandates this feature, meaning that applications using this > profile expects 64 bytes cache blocks. > > To make the upcoming RVA22U64 implementation complete, we'll zic64b as > a 'named feature', not a regular extension. This means that: > > - it won't be exposed to users; > - it won't be written in riscv,isa. > > This will be extended to other named extensions in the future, so we're > creating some common boilerplate for them as well. > > zic64b is default to 'true' since we're already using 64 bytes blocks. > If any cache block size (cbo{m,p,z}_blocksize) is changed to something > different than 64, zic64b is set to 'false'. > > Our profile implementation will then be able to check the current state > of zic64b and take the appropriate action (e.g. throw a warning). > > [1] > https://github.com/riscv/riscv-profiles/releases/download/v1.0/profiles.pdf > > Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> > Reviewed-by: Andrew Jones <ajo...@ventanamicro.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu.c | 6 ++++++ > target/riscv/cpu.h | 1 + > target/riscv/cpu_cfg.h | 1 + > target/riscv/tcg/tcg-cpu.c | 26 ++++++++++++++++++++++++++ > 4 files changed, 34 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 86e3514cc8..b2e539f807 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -1444,6 +1444,12 @@ const RISCVCPUMultiExtConfig > riscv_cpu_experimental_exts[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > +const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = { > + MULTI_EXT_CFG_BOOL("zic64b", zic64b, true), > + > + DEFINE_PROP_END_OF_LIST(), > +}; > + > /* Deprecated entries marked for future removal */ > const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = { > MULTI_EXT_CFG_BOOL("Zifencei", ext_zifencei, true), > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index d74b361be6..5fb4ca2324 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -767,6 +767,7 @@ typedef struct RISCVCPUMultiExtConfig { > extern const RISCVCPUMultiExtConfig riscv_cpu_extensions[]; > extern const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[]; > extern const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[]; > +extern const RISCVCPUMultiExtConfig riscv_cpu_named_features[]; > extern const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[]; > extern Property riscv_cpu_options[]; > > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index bd2ff87cc8..90f18eb601 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -116,6 +116,7 @@ struct RISCVCPUConfig { > bool ext_smepmp; > bool rvv_ta_all_1s; > bool rvv_ma_all_1s; > + bool zic64b; > > uint32_t mvendorid; > uint64_t marchid; > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index aee98db6f8..3319ba8e4e 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -114,6 +114,19 @@ static int cpu_cfg_ext_get_min_version(uint32_t > ext_offset) > g_assert_not_reached(); > } > > +static bool cpu_cfg_offset_is_named_feat(uint32_t ext_offset) > +{ > + const RISCVCPUMultiExtConfig *feat; > + > + for (feat = riscv_cpu_named_features; feat->name != NULL; feat++) { > + if (feat->offset == ext_offset) { > + return true; > + } > + } > + > + return false; > +} > + > static void cpu_bump_multi_ext_priv_ver(CPURISCVState *env, > uint32_t ext_offset) > { > @@ -123,6 +136,10 @@ static void cpu_bump_multi_ext_priv_ver(CPURISCVState > *env, > return; > } > > + if (cpu_cfg_offset_is_named_feat(ext_offset)) { > + return; > + } > + > ext_priv_ver = cpu_cfg_ext_get_min_version(ext_offset); > > if (env->priv_ver < ext_priv_ver) { > @@ -293,6 +310,13 @@ static void > riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) > } > } > > +static void riscv_cpu_update_named_features(RISCVCPU *cpu) > +{ > + cpu->cfg.zic64b = cpu->cfg.cbom_blocksize == 64 && > + cpu->cfg.cbop_blocksize == 64 && > + cpu->cfg.cboz_blocksize == 64; > +} > + > /* > * Check consistency between chosen extensions while setting > * cpu->cfg accordingly. > @@ -657,6 +681,8 @@ void riscv_tcg_cpu_finalize_features(RISCVCPU *cpu, Error > **errp) > return; > } > > + riscv_cpu_update_named_features(cpu); > + > if (cpu->cfg.ext_smepmp && !cpu->cfg.pmp) { > /* > * Enhanced PMP should only be available > -- > 2.43.0 > >