On Tue, 19 Dec 2023 at 21:33, Nabih Estefan <nabiheste...@google.com> wrote:
>
> From: Nabih Estefan Diaz <nabiheste...@google.com>
>
> Implemented Classes and Masks for GMAC Descriptors
> - Implemeted classes for GMAC Receive and Transmit Descriptors
> - Implemented Masks for said descriptors
>
> - General GMAC Register handling
> - GMAC IRQ Handling
>
This commit message doesn't match the changes in the patch:
it claims it's adding a lot more than it actually does.
> Signed-off-by: Nabih Estefan <nabiheste...@google.com>
> Reviewed-by: Tyrone Ting <kft...@nuvoton.com>
> ---
> hw/net/npcm_gmac.c | 40 ++++++++++++++++++++++++++++++++++++++++
> hw/net/trace-events | 8 ++++++++
> 2 files changed, 48 insertions(+)
>
> diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c
> index 98b3c33c94..44c4ffaff4 100644
> --- a/hw/net/npcm_gmac.c
> +++ b/hw/net/npcm_gmac.c
> @@ -149,6 +149,46 @@ static bool gmac_can_receive(NetClientState *nc)
> return true;
> }
>
> +/*
> + * Function that updates the GMAC IRQ
> + * It find the logical OR of the enabled bits for NIS (if enabled)
> + * It find the logical OR of the enabled bits for AIS (if enabled)
> + */
> +static void gmac_update_irq(NPCMGMACState *gmac)
> +{
> + /*
> + * Check if the normal interrupts summary is enabled
> + * if so, add the bits for the summary that are enabled
> + */
> + if (gmac->regs[R_NPCM_DMA_INTR_ENA] & gmac->regs[R_NPCM_DMA_STATUS] &
> + (NPCM_DMA_INTR_ENAB_NIE_BITS)) {
> + gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_NIS;
> + }
> + /*
> + * Check if the abnormal interrupts summary is enabled
> + * if so, add the bits for the summary that are enabled
> + */
> + if (gmac->regs[R_NPCM_DMA_INTR_ENA] & gmac->regs[R_NPCM_DMA_STATUS] &
> + (NPCM_DMA_INTR_ENAB_AIE_BITS)) {
> + gmac->regs[R_NPCM_DMA_STATUS] |= NPCM_DMA_STATUS_AIS;
> + }
> +
> + /* Get the logical OR of both normal and abnormal interrupts */
> + int level = !!((gmac->regs[R_NPCM_DMA_STATUS] &
> + gmac->regs[R_NPCM_DMA_INTR_ENA] &
> + NPCM_DMA_STATUS_NIS) |
> + (gmac->regs[R_NPCM_DMA_STATUS] &
> + gmac->regs[R_NPCM_DMA_INTR_ENA] &
> + NPCM_DMA_STATUS_AIS));
> +
> + /* Set the IRQ */
> + trace_npcm_gmac_update_irq(DEVICE(gmac)->canonical_path,
> + gmac->regs[R_NPCM_DMA_STATUS],
> + gmac->regs[R_NPCM_DMA_INTR_ENA],
> + level);
> + qemu_set_irq(gmac->irq, level);
> +}
> +
> static ssize_t gmac_receive(NetClientState *nc, const uint8_t *buf, size_t
> len)
> {
> /* Placeholder. Function will be filled in following patches */
> diff --git a/hw/net/trace-events b/hw/net/trace-events
> index 33514548b8..78efa2ec2c 100644
> --- a/hw/net/trace-events
> +++ b/hw/net/trace-events
> @@ -473,6 +473,14 @@ npcm_gmac_reg_write(const char *name, uint64_t offset,
> uint32_t value) "%s: offs
> npcm_gmac_mdio_access(const char *name, uint8_t is_write, uint8_t pa,
> uint8_t gr, uint16_t val) "%s: is_write: %" PRIu8 " pa: %" PRIu8 " gr: %"
> PRIu8 " val: 0x%04" PRIx16
> npcm_gmac_reset(const char *name, uint16_t value) "%s: phy_regs[0][1]:
> 0x%04" PRIx16
> npcm_gmac_set_link(bool active) "Set link: active=%u"
> +npcm_gmac_update_irq(const char *name, uint32_t status, uint32_t intr_en,
> int level) "%s: Status Reg: 0x%04" PRIX32 " Interrupt Enable Reg: 0x%04"
> PRIX32 " IRQ Set: %d"
> +npcm_gmac_packet_desc_read(const char* name, uint32_t desc_addr) "%s:
> attempting to read descriptor @0x%04" PRIX32
> +npcm_gmac_packet_receive(const char* name, uint32_t len) "%s: RX packet
> length: 0x%04" PRIX32
> +npcm_gmac_packet_receiving_buffer(const char* name, uint32_t buf_len,
> uint32_t rx_buf_addr) "%s: Receiving into Buffer size: 0x%04" PRIX32 " at
> address 0x%04" PRIX32
> +npcm_gmac_packet_received(const char* name, uint32_t len) "%s: Reception
> finished, packet left: 0x%04" PRIX32
> +npcm_gmac_packet_sent(const char* name, uint16_t len) "%s: TX packet sent!,
> length: 0x%04" PRIX16
> +npcm_gmac_debug_desc_data(const char* name, void* addr, uint32_t des0,
> uint32_t des1, uint32_t des2, uint32_t des3)"%s: Address: %p Descriptor 0:
> 0x%04" PRIX32 " Descriptor 1: 0x%04" PRIX32 "Descriptor 2: 0x%04" PRIX32 "
> Descriptor 3: 0x%04" PRIX32
> +npcm_gmac_packet_tx_desc_data(const char* name, uint32_t tdes0, uint32_t
> tdes1) "%s: Tdes0: 0x%04" PRIX32 " Tdes1: 0x%04" PRIX32
Most of these trace events don't correspond to the code change
in the patch; they should be added in the same patch which adds
the call to the trace event.
thanks
-- PMM
