From: Yu Zhang <yu.c.zh...@linux.intel.com>
Currently we use only VTD_FR_PASID_TABLE_INV as
fault reaon. Fix this with correct fault reasons
listed in VT-d spec 7.2.3.
Signed-off-by: Yu Zhang <yu.c.zh...@linux.intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.d...@intel.com>
---
hw/i386/intel_iommu_internal.h | 8 ++++++-
hw/i386/intel_iommu.c | 42 +++++++++++++++++++++-------------
2 files changed, 33 insertions(+), 17 deletions(-)
diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 41b958cd5d..21fa767740 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -325,8 +325,14 @@ typedef enum VTDFaultReason {
* request while disabled */
VTD_FR_IR_SID_ERR = 0x26, /* Invalid Source-ID */
- VTD_FR_PASID_TABLE_INV = 0x58, /*Invalid PASID table entry */
+ VTD_FR_RTADDR_INV_TTM = 0x31, /* Invalid TTM in RTADDR */
+ /* PASID directory entry access failure */
+ VTD_FR_PASID_DIR_ACCESS_ERR = 0x50,
+ /* The Present(P) field of pasid directory entry is 0 */
+ VTD_FR_PASID_DIR_ENTRY_P = 0x51,
+ VTD_FR_PASID_TABLE_ACCESS_ERR = 0x58, /* PASID table entry access failure
*/
VTD_FR_PASID_ENTRY_P = 0x59, /* The Present(P) field of pasidt-entry is 0
*/
+ VTD_FR_PASID_TABLE_ENTRY_INV = 0x5b, /*Invalid PASID table entry */
/* Output address in the interrupt address range for scalable mode */
VTD_FR_SM_INTERRUPT_ADDR = 0x87,
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 1c21f40ccd..1e87383a41 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -819,7 +819,7 @@ static int vtd_get_pdire_from_pdir_table(dma_addr_t
pasid_dir_base,
addr = pasid_dir_base + index * entry_size;
if (dma_memory_read(&address_space_memory, addr,
pdire, entry_size, MEMTXATTRS_UNSPECIFIED)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_DIR_ACCESS_ERR;
}
pdire->val = le64_to_cpu(pdire->val);
@@ -832,6 +832,11 @@ static inline bool vtd_pe_present(VTDPASIDEntry *pe)
return pe->val[0] & VTD_PASID_ENTRY_P;
}
+static inline uint32_t vtd_pe_get_flpt_level(VTDPASIDEntry *pe)
+{
+ return 4 + ((pe->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM);
+}
+
static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState *s,
uint32_t pasid,
dma_addr_t addr,
@@ -840,13 +845,14 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState
*s,
uint32_t index;
dma_addr_t entry_size;
X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
+ uint8_t pgtt;
index = VTD_PASID_TABLE_INDEX(pasid);
entry_size = VTD_PASID_ENTRY_SIZE;
addr = addr + index * entry_size;
if (dma_memory_read(&address_space_memory, addr,
pe, entry_size, MEMTXATTRS_UNSPECIFIED)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_TABLE_ACCESS_ERR;
}
for (size_t i = 0; i < ARRAY_SIZE(pe->val); i++) {
pe->val[i] = le64_to_cpu(pe->val[i]);
@@ -854,12 +860,17 @@ static int vtd_get_pe_in_pasid_leaf_table(IntelIOMMUState
*s,
/* Do translation type check */
if (!vtd_pe_type_check(x86_iommu, pe)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_TABLE_ENTRY_INV;
}
- if (!vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe))) {
- return -VTD_FR_PASID_TABLE_INV;
- }
+ pgtt = VTD_PE_GET_TYPE(pe);
+ if (pgtt == VTD_SM_PASID_ENTRY_SLT &&
+ !vtd_is_level_supported(s, VTD_PE_GET_LEVEL(pe)))
+ return -VTD_FR_PASID_TABLE_ENTRY_INV;
+
+ if (pgtt == VTD_SM_PASID_ENTRY_FLT &&
+ vtd_pe_get_flpt_level(pe) != 4)
+ return -VTD_FR_PASID_TABLE_ENTRY_INV;
return 0;
}
@@ -899,7 +910,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s,
}
if (!vtd_pdire_present(&pdire)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_DIR_ENTRY_P;
}
ret = vtd_get_pe_from_pdire(s, pasid, &pdire, pe);
@@ -908,7 +919,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState *s,
}
if (!vtd_pe_present(pe)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_ENTRY_P;
}
return 0;
@@ -961,7 +972,7 @@ static int vtd_ce_get_pasid_fpd(IntelIOMMUState *s,
}
if (!vtd_pdire_present(&pdire)) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_PASID_DIR_ENTRY_P;
}
/*
@@ -1829,7 +1840,11 @@ static const bool vtd_qualified_faults[] = {
[VTD_FR_ROOT_ENTRY_RSVD] = false,
[VTD_FR_PAGING_ENTRY_RSVD] = true,
[VTD_FR_CONTEXT_ENTRY_TT] = true,
- [VTD_FR_PASID_TABLE_INV] = false,
+ [VTD_FR_PASID_DIR_ACCESS_ERR] = false,
+ [VTD_FR_PASID_DIR_ENTRY_P] = true,
+ [VTD_FR_PASID_TABLE_ACCESS_ERR] = false,
+ [VTD_FR_PASID_ENTRY_P] = true,
+ [VTD_FR_PASID_TABLE_ENTRY_INV] = true,
[VTD_FR_SM_INTERRUPT_ADDR] = true,
[VTD_FR_MAX] = false,
};
@@ -1904,11 +1919,6 @@ static inline uint64_t vtd_flpt_level_page_mask(uint32_t
level)
return ~((1ULL << vtd_flpt_level_shift(level)) - 1);
}
-static inline dma_addr_t vtd_pe_get_flpt_level(VTDPASIDEntry *pe)
-{
- return 4 + ((pe->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM);
-}
-
/*
* Given an iova and the level of paging structure, return the offset
* of current level.
@@ -3499,7 +3509,7 @@ static inline int
vtd_dev_get_pe_from_pasid(IntelIOMMUState *s,
dma_addr_t pasid_dir_base;
if (!s->root_scalable) {
- return -VTD_FR_PASID_TABLE_INV;
+ return -VTD_FR_RTADDR_INV_TTM;
}
ret = vtd_dev_to_context_entry(s, bus_num, devfn, &ce);
--
2.34.1
