On Wed, Jan 17, 2024 at 07:54:12PM +0530, Himanshu Chauhan wrote: > This patch adds "x-sdtrig" in the ISA string when sdtrig extension is enabled. > The sdtrig extension may or may not be implemented in a system. Therefore, the > -cpu rv64,x-sdtrig=<true/false> > option can be used to dynamically turn sdtrig extension on or off. > > Signed-off-by: Himanshu Chauhan <hchau...@ventanamicro.com> > --- > target/riscv/cpu.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index c770a7e506..860e520730 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -153,6 +153,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), > ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), > ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), > + ISA_EXT_DATA_ENTRY(x-sdtrig, PRIV_VERSION_1_12_0, ext_sdtrig), > ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), > ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), > ISA_EXT_DATA_ENTRY(xtheadbs, PRIV_VERSION_1_11_0, ext_xtheadbs), > -- > 2.34.1 > >
We don't want the 'x-' part to show up in the ISA string. isa_edata_arr[] should get an entry without x-, and the x- property should be added to riscv_cpu_experimental_exts[]. Thanks, drew