On Fri, 19 Jan 2024 at 20:33, Nabih Estefan <nabiheste...@google.com> wrote: > > From: Hao Wu <wuhao...@google.com> > > The PCI Mailbox Module is a high-bandwidth communcation module > between a Nuvoton BMC and CPU. It features 16KB RAM that are both > accessible by the BMC and core CPU. and supports interrupt for > both sides. > > This patch implements the BMC side of the PCI mailbox module. > Communication with the core CPU is emulated via a chardev and > will be in a follow-up patch. > > Change-Id: Iaca22f81c4526927d437aa367079ed038faf43f2 > Signed-off-by: Hao Wu <wuhao...@google.com> > Signed-off-by: Nabih Estefan <nabiheste...@google.com> > Reviewed-by: Tyrone Ting <kft...@nuvoton.com>
Can we have a comment or other documentation defining what the protocol expected on the chardev device is, please? Without that it's hard to review to see whether the implementation is doing what it is supposed to. thanks -- PMM
