Re: [PATCH v3 02/13] target/riscv/csr.c: use 'vlenb' instead of 'vlen'

[Alistair Francis]

On Wed, Jan 17, 2024 at 7:00 AM Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
> As a bonus, we're being more idiomatic using cpu->cfg.vlenb when
> reading CSR_VLENB.
>
> Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
> Reviewed-by: Richard Henderson <richard.hender...@linaro.org>

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

> ---
>  target/riscv/csr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 674ea075a4..5c8d22452b 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -683,7 +683,7 @@ static RISCVException read_vl(CPURISCVState *env, int 
> csrno,
>
>  static int read_vlenb(CPURISCVState *env, int csrno, target_ulong *val)
>  {
> -    *val = riscv_cpu_cfg(env)->vlen >> 3;
> +    *val = riscv_cpu_cfg(env)->vlenb;
>      return RISCV_EXCP_NONE;
>  }
>
> @@ -738,7 +738,7 @@ static RISCVException write_vstart(CPURISCVState *env, 
> int csrno,
>       * The vstart CSR is defined to have only enough writable bits
>       * to hold the largest element index, i.e. lg2(VLEN) bits.
>       */
> -    env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlen));
> +    env->vstart = val & ~(~0ULL << ctzl(riscv_cpu_cfg(env)->vlenb << 3));
>      return RISCV_EXCP_NONE;
>  }
>
> --
> 2.43.0
>
>