On Tue, Jan 9, 2024 at 11:04 AM Atish Patra <ati...@rivosinc.com> wrote: > > From: Kaiwen Xue <kaiw...@rivosinc.com> > > This adds the properties for ISA extension smcntrpmf. Patches > implementing it will follow. > > Signed-off-by: Atish Patra <ati...@rivosinc.com> > Signed-off-by: Kaiwen Xue <kaiw...@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Alistair > --- > target/riscv/cpu.c | 2 ++ > target/riscv/cpu_cfg.h | 1 + > 2 files changed, 3 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 83c7c0cf07be..501ae560ec29 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -144,6 +144,7 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > ISA_EXT_DATA_ENTRY(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), > ISA_EXT_DATA_ENTRY(smaia, PRIV_VERSION_1_12_0, ext_smaia), > + ISA_EXT_DATA_ENTRY(smcntrpmf, PRIV_VERSION_1_12_0, ext_smcntrpmf), > ISA_EXT_DATA_ENTRY(smepmp, PRIV_VERSION_1_12_0, ext_smepmp), > ISA_EXT_DATA_ENTRY(smstateen, PRIV_VERSION_1_12_0, ext_smstateen), > ISA_EXT_DATA_ENTRY(ssaia, PRIV_VERSION_1_12_0, ext_ssaia), > @@ -1296,6 +1297,7 @@ const char *riscv_get_misa_ext_description(uint32_t bit) > const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { > /* Defaults for standard extensions */ > MULTI_EXT_CFG_BOOL("sscofpmf", ext_sscofpmf, false), > + MULTI_EXT_CFG_BOOL("smcntrpmf", ext_smcntrpmf, false), > MULTI_EXT_CFG_BOOL("zifencei", ext_zifencei, true), > MULTI_EXT_CFG_BOOL("zicsr", ext_zicsr, true), > MULTI_EXT_CFG_BOOL("zihintntl", ext_zihintntl, true), > diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h > index f4605fb190b9..00c34fdd3209 100644 > --- a/target/riscv/cpu_cfg.h > +++ b/target/riscv/cpu_cfg.h > @@ -72,6 +72,7 @@ struct RISCVCPUConfig { > bool ext_zihpm; > bool ext_smstateen; > bool ext_sstc; > + bool ext_smcntrpmf; > bool ext_svadu; > bool ext_svinval; > bool ext_svnapot; > -- > 2.34.1 > >