On Tue, Jan 2, 2024 at 7:22 PM Nati Rapaport <rapap...@cadence.com> wrote: > > Hello, > > I’m going to add some custom CSRs (Control & Status Registers) to a new RiscV > core in qemu. > > Could you please help me understanding if there is any method to do it?
Have a look at decode_opc() in target/riscv/translate.c. We probably want something similar where we can iterate over the vendor enabled CSRs. > > Should I do it in /target/riscv/cpu_bits.h where all CSRs are defined (and > other files, where all standard CSRs implementation reside?) and just put it > under a compilation flag for our new core only? The vendor CSRs should be in their own file. The idea is to keep as much as possible separated from the general RISC-V code. > > I don’t think so.. as I don’t see any similar example for that there. > > Should I add all the related code around these CSRs in dedicated source files > and let them built only for our core? Pretty much, although it will be built by default. We don't want custom binaries for vendors or anything like that Alistair > > Please explain.. > > > > Thank you in advance. > > Nati Rapaport > > Cadence Design Systems