On 1/24/24 02:03, Peter Maydell wrote:
A typo in the implementation of isar_feature_aa64_tidcp1() means we
were checking the field in the wrong ID register, so we might have
provided the feature on CPUs that don't have it and not provided
it on CPUs that should have it. Correct this bug.
Cc:[email protected]
Fixes: 9cd0c0dec97be9 "target/arm: Implement FEAT_TIDCP1"
Resolves:https://gitlab.com/qemu-project/qemu/-/issues/2120
Signed-off-by: Peter Maydell<[email protected]>
---
target/arm/cpu-features.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <[email protected]>
r~
