From: Daniel Henrique Barboza <dbarb...@ventanamicro.com> user_spec, bext_spec and bext_ver aren't being used.
Signed-off-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Tested-by: Vladimir Isaev <vladimir.is...@syntacore.com> Message-ID: <20240105230546.265053-2-dbarb...@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> --- target/riscv/cpu.h | 1 - target/riscv/cpu_cfg.h | 2 -- 2 files changed, 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 136fc1de73..52648e3af0 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -181,7 +181,6 @@ struct CPUArchState { target_ulong guest_phys_fault_addr; target_ulong priv_ver; - target_ulong bext_ver; target_ulong vext_ver; /* RISCVMXL, but uint32_t for vmstate migration */ diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 780ae6ef17..0612668144 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -140,8 +140,6 @@ struct RISCVCPUConfig { uint32_t pmu_mask; char *priv_spec; - char *user_spec; - char *bext_spec; char *vext_spec; uint16_t vlen; uint16_t elen; -- 2.43.0