The NMI exception state include whether the interrupt with super priority
is IRQ or FIQ, so add a nmi_is_irq flag in CPUARMState to distinguish it.
Signed-off-by: Jinjie Ruan <ruanjin...@huawei.com>
---
target/arm/cpu.h | 2 ++
target/arm/helper.c | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 5257343bcb..051e589e19 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -603,6 +603,8 @@ typedef struct CPUArchState {
/* State of our input IRQ/FIQ/VIRQ/VFIQ lines */
uint32_t irq_line_state;
+ bool nmi_is_irq;
+
/* Thumb-2 EE state. */
uint32_t teecr;
uint32_t teehbr;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index bd7858e02e..0bd7a87e51 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -10575,6 +10575,15 @@ uint32_t arm_phys_excp_target_el(CPUState *cs,
uint32_t excp_idx,
scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
hcr = hcr_el2 & HCR_FMO;
break;
+ case EXCP_NMI:
+ if (env->nmi_is_irq) {
+ scr = ((env->cp15.scr_el3 & SCR_IRQ) == SCR_IRQ);
+ hcr = hcr_el2 & HCR_IMO;
+ } else {
+ scr = ((env->cp15.scr_el3 & SCR_FIQ) == SCR_FIQ);
+ hcr = hcr_el2 & HCR_FMO;
+ }
+ break;
default:
scr = ((env->cp15.scr_el3 & SCR_EA) == SCR_EA);
hcr = hcr_el2 & HCR_AMO;
--
2.34.1
