Signed-off-by: Jason Chien <jason.ch...@sifive.com> Reviewed-by: Frank Chang <frank.ch...@sifive.com> Reviewed-by: Max Chou <max.c...@sifive.com> --- target/riscv/cpu.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 851ac7372c..6bd8798bb5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -1473,6 +1473,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zfh", ext_zfh, false), MULTI_EXT_CFG_BOOL("zfhmin", ext_zfhmin, false), MULTI_EXT_CFG_BOOL("zve32f", ext_zve32f, false), + MULTI_EXT_CFG_BOOL("zve32x", ext_zve32x, false), MULTI_EXT_CFG_BOOL("zve64f", ext_zve64f, false), MULTI_EXT_CFG_BOOL("zve64d", ext_zve64d, false), MULTI_EXT_CFG_BOOL("zvfbfmin", ext_zvfbfmin, false), -- 2.43.2