On 2024/3/28 18:57, Michael S. Tsirkin wrote:
> On Thu, Mar 28, 2024 at 06:39:03PM +0800, Jiqian Chen wrote:
>> In current code, when guest does S3, virtio devices are reset due to
>> the bit No_Soft_Reset is not set. After resetting, the display resources
>> of virtio-gpu are destroyed, then the display can't come back and only
>> show blank after resuming.
>>
>> Implement No_Soft_Reset bit of PCI_PM_CTRL register, then guest can check
>> this bit, if this bit is set, the devices resetting will not be done, and
>> then the display can work after resuming.
>>
>> Signed-off-by: Jiqian Chen <jiqian.c...@amd.com>
>> ---
>> hw/virtio/virtio-pci.c | 29 +++++++++++++++++++++++++++++
>> include/hw/virtio/virtio-pci.h | 5 +++++
>> 2 files changed, 34 insertions(+)
>>
>> diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c
>> index 05dd03758d9f..8d9fab855c7d 100644
>> --- a/hw/virtio/virtio-pci.c
>> +++ b/hw/virtio/virtio-pci.c
>> @@ -2378,6 +2378,11 @@ static void virtio_pci_realize(PCIDevice *pci_dev,
>> Error **errp)
>> pcie_cap_lnkctl_init(pci_dev);
>> }
>>
>> + if (proxy->flags & VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET) {
>> + pci_set_word(pci_dev->config + pos + PCI_PM_CTRL,
>> + PCI_PM_CTRL_NO_SOFT_RESET);
>> + }
>> +
>> if (proxy->flags & VIRTIO_PCI_FLAG_INIT_PM) {
>> /* Init Power Management Control Register */
>> pci_set_word(pci_dev->wmask + pos + PCI_PM_CTRL,
>> @@ -2440,11 +2445,33 @@ static void virtio_pci_reset(DeviceState *qdev)
>> }
>> }
>>
>> +static bool virtio_pci_no_soft_reset(PCIDevice *dev)
>> +{
>> + uint16_t pmcsr;
>> +
>> + if (!pci_is_express(dev) || !dev->exp.pm_cap) {
>> + return false;
>> + }
>> +
>> + pmcsr = pci_get_word(dev->config + dev->exp.pm_cap + PCI_PM_CTRL);
>> +
>> + /*
>> + * When No_Soft_Reset bit is set and the device
>> + * is in D3hot state, don't reset device
>> + */
>> + return ((pmcsr & PCI_PM_CTRL_NO_SOFT_RESET) &&
>> + (pmcsr & PCI_PM_CTRL_STATE_MASK) == 3);
>
>
> No need for () around return value.
Ok, will delete in next version.
>
>> +}
>> +
>> static void virtio_pci_bus_reset_hold(Object *obj)
>> {
>> PCIDevice *dev = PCI_DEVICE(obj);
>> DeviceState *qdev = DEVICE(obj);
>>
>> + if (virtio_pci_no_soft_reset(dev)) {
>> + return;
>> + }
>> +
>> virtio_pci_reset(qdev);
>>
>> if (pci_is_express(dev)) {
>> @@ -2484,6 +2511,8 @@ static Property virtio_pci_properties[] = {
>> VIRTIO_PCI_FLAG_INIT_LNKCTL_BIT, true),
>> DEFINE_PROP_BIT("x-pcie-pm-init", VirtIOPCIProxy, flags,
>> VIRTIO_PCI_FLAG_INIT_PM_BIT, true),
>> + DEFINE_PROP_BIT("x-pcie-pm-no-soft-reset", VirtIOPCIProxy, flags,
>> + VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT, false),
>> DEFINE_PROP_BIT("x-pcie-flr-init", VirtIOPCIProxy, flags,
>> VIRTIO_PCI_FLAG_INIT_FLR_BIT, true),
>> DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags,
>
> I am a bit confused about this part.
> Do you want to make this software controllable?
Yes, because even the real hardware, this bit is not always set.
> Or should this be set to true by default and then
> changed to false for old machine types?
How can I do so?
Do you mean set this to true by default, and if old machine types don't need
this bit, they can pass false config to qemu when running qemu?
>
>
>> diff --git a/include/hw/virtio/virtio-pci.h b/include/hw/virtio/virtio-pci.h
>> index 4d57a9c75130..c758eb738234 100644
>> --- a/include/hw/virtio/virtio-pci.h
>> +++ b/include/hw/virtio/virtio-pci.h
>> @@ -44,6 +44,7 @@ enum {
>> VIRTIO_PCI_FLAG_AER_BIT,
>> VIRTIO_PCI_FLAG_ATS_PAGE_ALIGNED_BIT,
>> VIRTIO_PCI_FLAG_VDPA_BIT,
>> + VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT,
>> };
>>
>> /* Need to activate work-arounds for buggy guests at vmstate load. */
>> @@ -80,6 +81,10 @@ enum {
>> /* Init Power Management */
>> #define VIRTIO_PCI_FLAG_INIT_PM (1 << VIRTIO_PCI_FLAG_INIT_PM_BIT)
>>
>> +/* Init The No_Soft_Reset bit of Power Management */
>> +#define VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET \
>> + (1 << VIRTIO_PCI_FLAG_PM_NO_SOFT_RESET_BIT)
>> +
>> /* Init Function Level Reset capability */
>> #define VIRTIO_PCI_FLAG_INIT_FLR (1 << VIRTIO_PCI_FLAG_INIT_FLR_BIT)
>>
>> --
>> 2.34.1
>
--
Best regards,
Jiqian Chen.
