Vexpress motherboard has two 2x16 NOR flash, but pflash_cfi01 doesn't support interleaving, so here only models two 1x32 flash. Although it's not exactly modeled, it works fine for running linux.
Signed-off-by: Liming Wang <walimis...@gmail.com> --- hw/vexpress.c | 19 +++++++++++++++++-- 1 files changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/vexpress.c b/hw/vexpress.c index b9aafec..921b01b 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -29,9 +29,13 @@ #include "sysemu.h" #include "boards.h" #include "exec-memory.h" +#include "flash.h" +#include "blockdev.h" #define VEXPRESS_BOARD_ID 0x8e0 +#define VEXPRESS_FLASH_SIZE 0x04000000 + static struct arm_boot_info vexpress_binfo; /* Address maps for peripherals: @@ -355,6 +359,9 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard, MemoryRegion *vram = g_new(MemoryRegion, 1); MemoryRegion *sram = g_new(MemoryRegion, 1); const target_phys_addr_t *map = daughterboard->motherboard_map; + DriveInfo *dinfo = NULL; + uint32_t sector_len = 256 * 1024; + int i = 0; daughterboard->init(daughterboard, ram_size, cpu_model, pic, &proc_id); @@ -405,9 +412,17 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard, sysbus_create_simple("pl111", map[VE_CLCD], pic[14]); - /* VE_NORFLASH0: not modelled */ + for(i = 0; i < 2; i++) { + dinfo = drive_get(IF_PFLASH, 0, i); + if (dinfo) { + pflash_cfi01_register(((i == 0) ? map[VE_NORFLASH0] : map[VE_NORFLASH1]), NULL, + ((i == 0) ? "vexpress.flash0" : "vexpress:flash1"), + VEXPRESS_FLASH_SIZE, dinfo->bdrv, sector_len, + VEXPRESS_FLASH_SIZE / sector_len, 4, + 0, 0x89, 0x89, 0x19, 0); + } + } /* VE_NORFLASH0ALIAS: not modelled */ - /* VE_NORFLASH1: not modelled */ sram_size = 0x2000000; memory_region_init_ram(sram, "vexpress.sram", sram_size); -- 1.7.0.4