On 4/16/24 16:04, Daniel Henrique Barboza wrote:
Privileged spec section 4.1.9 mentions:
"When a trap is taken into S-mode, stval is written with
exception-specific information to assist software in handling the trap.
(...)
If stval is written with a nonzero value when a breakpoint,
address-misaligned, access-fault, or page-fault exception occurs on an
instruction fetch, load, or store, then stval will contain the faulting
virtual address."
A similar text is found for mtval in section 3.1.16.
Setting mtval/stval in this scenario is optional, but some softwares read
these regs when handling ebreaks.
Write 'badaddr' in all ebreak breakpoints to write the appropriate
'tval' during riscv_do_cpu_interrrupt().
Signed-off-by: Daniel Henrique Barboza<dbarb...@ventanamicro.com>
---
target/riscv/insn_trans/trans_privileged.c.inc | 2 ++
1 file changed, 2 insertions(+)
Reviewed-by: Richard Henderson <richard.hender...@linaro.org>
r~
