On 4/22/24 08:21, Richard Henderson wrote:
For Arm's CPUs they fall into two categories:
* older ones don't set MT in their MPIDR, and the Aff0
field is effectively the CPU number
* newer ones do set MT in their MPIDR, but don't have
SMT, so their Aff0 is always 0 and their Aff1
is the CPU number
Of all the CPUs we model, none of them are the
architecturally-permitted "MT is set, CPU implements
actual SMT, Aff0 indicates the thread in the CPU" type.
Looking at the TRM, Neoverse-E1 is "MT is set, actual SMT,
Aff0 is the thread" (Aff0 can be 0 or 1). We just don't
model that CPU type yet. But we should probably make
sure we don't block ourselves into a corner where that
would be awkward -- I'll have a think about this and
look at what x86 does with the topology info.
I'm suggesting that we set things up per -smp, and if the user chooses a -cpu value for
which that topology doesn't make sense, we do it anyway and let them keep both pieces.
... but more practically, it allows experimentation at -cpu max, without having to build
in anything cpu-specific. Good to know about the E1 though...
r~
