Set link width to x1 and link speed to 2.5 Gb/s as specified by the
datasheet. Without this, these fields in the link status register read
zero, which is incorrect.
This problem appeared since 3d67447fe7c2 ("pcie: Fill PCIESlot link fields
to support higher speeds and widths"), which allows PCIe slot to set link
width and link speed. However, if PCIe slot does not explicitly set these
properties, they will be zero. Before this commit, the width and speed
default to x1 and 2.5 Gb/s.
Fixes: 3d67447fe7c2 ("pcie: Fill PCIESlot link fields to support higher speeds
and widths")
Signed-off-by: Nam Cao <nam...@linutronix.de>
---
v2: implement this in .realize() instead
---
hw/pci-bridge/xio3130_downstream.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/pci-bridge/xio3130_downstream.c
b/hw/pci-bridge/xio3130_downstream.c
index 38a2361fa2..2df1ee203d 100644
--- a/hw/pci-bridge/xio3130_downstream.c
+++ b/hw/pci-bridge/xio3130_downstream.c
@@ -72,6 +72,9 @@ static void xio3130_downstream_realize(PCIDevice *d, Error
**errp)
pci_bridge_initfn(d, TYPE_PCIE_BUS);
pcie_port_init_reg(d);
+ s->speed = QEMU_PCI_EXP_LNK_2_5GT;
+ s->width = QEMU_PCI_EXP_LNK_X1;
+
rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
--
2.39.2
