On Tue, May 28, 2024 at 11:05 PM Jerry Zhang Jian
<jerry.zhangj...@sifive.com> wrote:
>
> - According to RISC-V crypto spec, Zvkb extension is a proper subset of the
> Zvbb extension.
>
> - Reference:
> https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10
>
> Signed-off-by: Jerry Zhang Jian <jerry.zhangj...@sifive.com>
When sending a new version can you please include all previous tags
(unless there are major changes)
Applied to riscv-to-apply.next
Alistair
> ---
> target/riscv/tcg/tcg-cpu.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 40054a391a..f1a1306ab2 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
> cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
> }
>
> + if (cpu->cfg.ext_zvbb) {
> + cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
> + }
> +
> /*
> * In principle Zve*x would also suffice here, were they supported
> * in qemu
> --
> 2.44.0
>
>
