On 5/28/24 3:41 AM, Eric Cheng wrote:
On 5/24/2024 1:39 AM, Daniel Henrique Barboza wrote:
...
+/* 5.4 Features control register (32bits) */
+#define RISCV_IOMMU_REG_FCTL 0x0008
Looks like doesn't support RISCV_IOMMU_FCTL_BE?
If so, need to implement it as read-only? along with other 2 bits.
Good point. Just set RISCV_IOMMU_FCTL_BE in regs_ro mask. I'll also set
FCTL_WSI given that, at this moment, we do not have wired interrupt
support (the riscv-iommu sysbus device will support it later).
FCTL_GSX is declared and used in patch 8 so we don't need to set it
as read-only. Thanks,
Daniel
IIUC,
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index 1b34d226f9..6a6bf1db98 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -2035,6 +2035,7 @@ static void riscv_iommu_realize(DeviceState *dev, Error
**errp)
/* Set power-on register state */
stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_CAP], s->cap);
stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_FCTL], 0);
+ stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_FCTL], ~0);
stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_DDTP],
~(RISCV_IOMMU_DDTP_PPN | RISCV_IOMMU_DDTP_MODE));
stq_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQB],
+#define RISCV_IOMMU_FCTL_WSI BIT(1)
+
...
