Based on discussions at [1] this is a simple conversion from using the RISC-V specific bit operations to using standard QEMU ones.
This series adds two new bit op helpers mask_extract64() and mask_deposit64() which the RISC-V target can then use. 1: https://mail.gnu.org/archive/html/qemu-devel/2024-07/msg05976.html Alistair Francis (2): include: bitops: Add mask extract64/deposit64 target/riscv: Remove get_field and set_field include/qemu/bitops.h | 35 +++++++++++++++++ target/riscv/cpu.h | 10 ++--- target/riscv/cpu_bits.h | 6 --- target/riscv/pmp.h | 6 +-- target/riscv/cpu.c | 20 +++++----- target/riscv/cpu_helper.c | 83 ++++++++++++++++++++------------------- target/riscv/csr.c | 82 +++++++++++++++++++------------------- target/riscv/debug.c | 14 +++---- target/riscv/monitor.c | 8 ++-- target/riscv/op_helper.c | 70 +++++++++++++++++---------------- target/riscv/pmu.c | 6 +-- target/riscv/zce_helper.c | 2 +- 12 files changed, 191 insertions(+), 151 deletions(-) -- 2.45.2
