Thanks for your previous reply. Here are some explanations for the previous questions: 1. In the previous version, the 'int flag' was used to distinguish whether an instruction was 'ld' or 'ldsp' for different processing. In this version, a boolean type 'is_1dsp' is defined to make the code clearer. 2. For the ldsp&sdsp instructions, since 'rs1=2' is defaulted during insn16 decoding, no additional processing is done in trans *.
Additional modifications in this version of the patch: 1. Zcmlsd renamed to zclsd. 2. Optimized the constraint rules of instructions on registers. 3. Adjustment of implicit relationship between zclsd and zca&zlsd. lxx (1): target/riscv: Add Zilsd and Zclsd extension support target/riscv/cpu.c | 4 + target/riscv/cpu_cfg.h | 2 + target/riscv/insn16.decode | 8 ++ target/riscv/insn32.decode | 12 ++- target/riscv/insn_trans/trans_zclsd.c.inc | 99 +++++++++++++++++++++++ target/riscv/insn_trans/trans_zilsd.c.inc | 89 ++++++++++++++++++++ target/riscv/tcg/tcg-cpu.c | 16 ++++ target/riscv/translate.c | 2 + 8 files changed, 230 insertions(+), 2 deletions(-) create mode 100644 target/riscv/insn_trans/trans_zclsd.c.inc create mode 100644 target/riscv/insn_trans/trans_zilsd.c.inc -- 2.45.2
