On Fri, Oct 18, 2024 at 12:54 AM Clément Léger <cle...@rivosinc.com> wrote:
>
> When the Ssdbltrp ISA extension is enabled, if a trap happens in S-mode
> while SSTATUS.SDT isn't cleared, generate a double trap exception to
> M-mode.
>
> Signed-off-by: Clément Léger <cle...@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.c | 2 +-
> target/riscv/cpu_bits.h | 1 +
> target/riscv/cpu_helper.c | 42 ++++++++++++++++++++++++++++++++++-----
> 3 files changed, 39 insertions(+), 6 deletions(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index fed64741d1..5224eb356d 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -285,7 +285,7 @@ static const char * const riscv_excp_names[] = {
> "load_page_fault",
> "reserved",
> "store_page_fault",
> - "reserved",
> + "double_trap",
> "reserved",
> "reserved",
> "reserved",
> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
> index 08cc5b2e22..0d0f253fcb 100644
> --- a/target/riscv/cpu_bits.h
> +++ b/target/riscv/cpu_bits.h
> @@ -699,6 +699,7 @@ typedef enum RISCVException {
> RISCV_EXCP_INST_PAGE_FAULT = 0xc, /* since: priv-1.10.0 */
> RISCV_EXCP_LOAD_PAGE_FAULT = 0xd, /* since: priv-1.10.0 */
> RISCV_EXCP_STORE_PAGE_FAULT = 0xf, /* since: priv-1.10.0 */
> + RISCV_EXCP_DOUBLE_TRAP = 0x10,
> RISCV_EXCP_SW_CHECK = 0x12, /* since: priv-1.13.0 */
> RISCV_EXCP_HW_ERR = 0x13, /* since: priv-1.13.0 */
> RISCV_EXCP_INST_GUEST_PAGE_FAULT = 0x14,
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index b9f36e8621..623a3abbf7 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1715,6 +1715,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> CPURISCVState *env = &cpu->env;
> bool virt = env->virt_enabled;
> bool write_gva = false;
> + bool vsmode_exc;
> uint64_t s;
> int mode;
>
> @@ -1729,6 +1730,8 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> !(env->mip & (1 << cause));
> bool vs_injected = env->hvip & (1 << cause) & env->hvien &&
> !(env->mip & (1 << cause));
> + bool smode_double_trap = false;
> + uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
> target_ulong tval = 0;
> target_ulong tinst = 0;
> target_ulong htval = 0;
> @@ -1839,13 +1842,34 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> mode = env->priv <= PRV_S && cause < 64 &&
> (((deleg >> cause) & 1) || s_injected || vs_injected) ? PRV_S :
> PRV_M;
>
> + vsmode_exc = env->virt_enabled && (((hdeleg >> cause) & 1) ||
> vs_injected);
> + /*
> + * Check double trap condition only if already in S-mode and targeting
> + * S-mode
> + */
> + if (cpu->cfg.ext_ssdbltrp && env->priv == PRV_S && mode == PRV_S) {
> + bool dte = (env->menvcfg & MENVCFG_DTE) != 0;
> + bool sdt = (env->mstatus & MSTATUS_SDT) != 0;
> + /* In VS or HS */
> + if (riscv_has_ext(env, RVH)) {
> + if (vsmode_exc) {
> + /* VS -> VS, use henvcfg instead of menvcfg*/
> + dte = (env->henvcfg & HENVCFG_DTE) != 0;
> + } else if (env->virt_enabled) {
> + /* VS -> HS, use mstatus_hs */
> + sdt = (env->mstatus_hs & MSTATUS_SDT) != 0;
> + }
> + }
> + smode_double_trap = dte && sdt;
> + if (smode_double_trap) {
> + mode = PRV_M;
> + }
> + }
> +
> if (mode == PRV_S) {
> /* handle the trap in S-mode */
> if (riscv_has_ext(env, RVH)) {
> - uint64_t hdeleg = async ? env->hideleg : env->hedeleg;
> -
> - if (env->virt_enabled &&
> - (((hdeleg >> cause) & 1) || vs_injected)) {
> + if (vsmode_exc) {
> /* Trap to VS mode */
> /*
> * See if we need to adjust cause. Yes if its VS mode
> interrupt
> @@ -1878,6 +1902,9 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> s = set_field(s, MSTATUS_SPIE, get_field(s, MSTATUS_SIE));
> s = set_field(s, MSTATUS_SPP, env->priv);
> s = set_field(s, MSTATUS_SIE, 0);
> + if (riscv_env_smode_dbltrp_enabled(env, virt)) {
> + s = set_field(s, MSTATUS_SDT, 1);
> + }
> env->mstatus = s;
> sxlen = 16 << riscv_cpu_sxl(env);
> env->scause = cause | ((target_ulong)async << (sxlen - 1));
> @@ -1913,9 +1940,14 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> env->mstatus = s;
> mxlen = 16 << riscv_cpu_mxl(env);
> env->mcause = cause | ((target_ulong)async << (mxlen - 1));
> + if (smode_double_trap) {
> + env->mtval2 = env->mcause;
> + env->mcause = RISCV_EXCP_DOUBLE_TRAP;
> + } else {
> + env->mtval2 = mtval2;
> + }
> env->mepc = env->pc;
> env->mtval = tval;
> - env->mtval2 = mtval2;
> env->mtinst = tinst;
>
> /*
> --
> 2.45.2
>
>
