On 12/11/24 16:41, Aleksandar Rakic wrote:
Enable MSA ASE for mips64R2-generic CPU.
Cherry-picked 60f6ae8d3d685ba1ea5d301222fb72b67f39264f
from https://github.com/MIPS/gnutools-qemu
Signed-off-by: Faraz Shahbazker <fshahbaz...@wavecomp.com>
Signed-off-by: Aleksandar Rakic <aleksandar.ra...@htecgroup.com>
---
target/mips/cpu-defs.c.inc | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc
index 922fc39138..e77a327422 100644
--- a/target/mips/cpu-defs.c.inc
+++ b/target/mips/cpu-defs.c.inc
@@ -678,7 +678,9 @@ const mips_def_t mips_defs[] =
(2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
(1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
.CP0_Config2 = MIPS_CONFIG2,
- .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
+ .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA) |
+ (1 << CP0C3_VInt) | (1 << CP0C3_MSAP),
+ .CP0_Config5_rw_bitmask = (1 << CP0C5_MSAEn),
See v2:
https://lore.kernel.org/qemu-devel/50dd60b2-f789-4828-9a7e-3becc6721...@linaro.org/
.CP0_LLAddr_rw_bitmask = 0,
.CP0_LLAddr_shift = 0,
.SYNCI_Step = 32,
