[PATCH 07/20] target/riscv: Implement CPUClass::datapath_is_big_endian

[Philippe Mathieu-Daudé]

While the RISC-V data endianness can be changed at runtime,
we do not implement that. The current translation code assumes
little-endian memory accesses (See commit a2f827ff4f4 "target/riscv:
accessors to registers upper part and 128-bit load/store").

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
 target/riscv/cpu.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f219f0c3b52..b31b9b3471d 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -60,6 +60,22 @@ bool riscv_cpu_is_32bit(RISCVCPU *cpu)
     return riscv_cpu_mxl(&cpu->env) == MXL_RV32;
 }
 
+static bool riscv_cpu_datapath_is_big_endian(CPUState *cs)
+{
+#ifndef CONFIG_USER_ONLY
+    /*
+     * A couple of bits in MSTATUS set the endianness:
+     *  - MSTATUS_UBE (User-mode),
+     *  - MSTATUS_SBE (Supervisor-mode),
+     *  - MSTATUS_MBE (Machine-mode)
+     * but we don't implement that yet.
+     */
+    return false;
+#else
+    return false;
+#endif
+}
+
 /* Hash that stores general user set numeric options */
 static GHashTable *general_user_opts;
 
@@ -2764,6 +2780,7 @@ static void riscv_cpu_common_class_init(ObjectClass *c, 
void *data)
                                        &mcc->parent_phases);
 
     cc->class_by_name = riscv_cpu_class_by_name;
+    cc->datapath_is_big_endian = riscv_cpu_datapath_is_big_endian;
     cc->has_work = riscv_cpu_has_work;
     cc->mmu_index = riscv_cpu_mmu_index;
     cc->dump_state = riscv_cpu_dump_state;
-- 
2.45.2