The GGC register at 0x50 of pci config space is a mirror of the same
register at 0x108040 of mmio bar0 [1]. i915 driver also reads that
register from mmio bar0 instead of config space. As GGC is programmed
and emulated by qemu, the mmio address should also be emulated, in the
same way of BDSM register.
[1] 4.1.28, 12th Generation Intel Core Processors Datasheet Volume 2
https://www.intel.com/content/www/us/en/content-details/655259
Signed-off-by: Tomita Moeko <tomitamo...@gmail.com>
---
hw/vfio/igd.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/hw/vfio/igd.c b/hw/vfio/igd.c
index 18d159aa8e..12e0553e83 100644
--- a/hw/vfio/igd.c
+++ b/hw/vfio/igd.c
@@ -488,8 +488,10 @@ static const MemoryRegionOps vfio_igd_quirk_mirror_##name
= { \
.endianness = DEVICE_LITTLE_ENDIAN, \
};
+VFIO_IGD_QUIRK_MIRROR_REG(IGD_GMCH, ggc)
VFIO_IGD_QUIRK_MIRROR_REG(IGD_BDSM_GEN11, bdsm)
+#define IGD_GGC_MMIO_OFFSET 0x108040
#define IGD_BDSM_MMIO_OFFSET 0x1080C0
void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int nr)
@@ -518,14 +520,21 @@ void vfio_probe_igd_bar0_quirk(VFIOPCIDevice *vdev, int
nr)
return;
}
- quirk = vfio_quirk_alloc(1);
+ quirk = vfio_quirk_alloc(2);
quirk->data = vdev;
memory_region_init_io(&quirk->mem[0], OBJECT(vdev),
+ &vfio_igd_quirk_mirror_ggc, vdev,
+ "vfio-igd-ggc-quirk", 2);
+ memory_region_add_subregion_overlap(vdev->bars[0].region.mem,
+ IGD_GGC_MMIO_OFFSET, &quirk->mem[0],
+ 1);
+
+ memory_region_init_io(&quirk->mem[1], OBJECT(vdev),
&vfio_igd_quirk_mirror_bdsm, vdev,
"vfio-igd-bdsm-quirk", 8);
memory_region_add_subregion_overlap(vdev->bars[0].region.mem,
- IGD_BDSM_MMIO_OFFSET, &quirk->mem[0],
+ IGD_BDSM_MMIO_OFFSET, &quirk->mem[1],
1);
QLIST_INSERT_HEAD(&vdev->bars[nr].quirks, quirk, next);
--
2.45.2
