On 12/6/2024 4:00 AM, Hendrik Wuethrich wrote:
From: ‪Hendrik Wüthrich <whend...@google.com>

Add RDT features to feature word / TCG.

Signed-off-by: Hendrik Wüthrich <whend...@google.com>
---
  target/i386/cpu.c | 30 ++++++++++++++++++++++++++++--
  target/i386/cpu.h |  2 ++
  2 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index bbe2da8ebb..5e29bf341c 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -869,7 +869,8 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
            CPUID_7_0_EBX_CLFLUSHOPT |            \
            CPUID_7_0_EBX_CLWB | CPUID_7_0_EBX_MPX | CPUID_7_0_EBX_FSGSBASE | \
            CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_RDSEED | \
-          CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES)
+          CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_KERNEL_FEATURES | \
+          CPUID_7_0_EBX_PQM | CPUID_7_0_EBX_PQE)
            /* missing:
            CPUID_7_0_EBX_HLE
            CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM */
@@ -906,6 +907,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
  #define TCG_SGX_12_0_EBX_FEATURES 0
  #define TCG_SGX_12_1_EAX_FEATURES 0
  #define TCG_24_0_EBX_FEATURES 0
+#define TCG_RDT_15_0_EDX_FEATURES CPUID_15_0_EDX_L3
#if defined CONFIG_USER_ONLY
  #define CPUID_8000_0008_EBX_KERNEL_FEATURES (CPUID_8000_0008_EBX_IBPB | \
@@ -1063,7 +1065,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
              "fsgsbase", "tsc-adjust", "sgx", "bmi1",
              "hle", "avx2", "fdp-excptn-only", "smep",
              "bmi2", "erms", "invpcid", "rtm",
-            NULL, "zero-fcs-fds", "mpx", NULL,
+            "rdt-m", "zero-fcs-fds", "mpx", "rdt-a",
              "avx512f", "avx512dq", "rdseed", "adx",
              "smap", "avx512ifma", "pcommit", "clflushopt",
              "clwb", "intel-pt", "avx512pf", "avx512er",
@@ -1651,6 +1653,30 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
          },
          .tcg_features = TCG_SGX_12_1_EAX_FEATURES,
      },
+
+    [FEAT_RDT_10_0_EBX] = {

Here 10 is hexadecimal, while ...

+        .type = CPUID_FEATURE_WORD,
+        .feat_names = {
+            NULL, "l3-cat", "l2-cat", "mba"
+        },
+        .cpuid = {
+            .eax = 0x10,
+            .needs_ecx = true, .ecx = 0,
+            .reg = R_EBX,
+        }
+    },
+    [FEAT_RDT_15_0_EDX] = {

... 15 is decimal, please make them consistent.

+        .type = CPUID_FEATURE_WORD,
+        .feat_names = {
+            [1] = "l3-cmt"
+        },
+        .cpuid = {
+            .eax = 0xf,
+            .needs_ecx = true, .ecx = 0,
+            .reg = R_EDX,
+        },
+        .tcg_features = TCG_RDT_15_0_EDX_FEATURES,
+    },
  };
typedef struct FeatureMask {
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 98407c8e18..37dc451e39 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -678,7 +678,9 @@ typedef enum FeatureWord {
      FEAT_7_1_EDX,       /* CPUID[EAX=7,ECX=1].EDX */
      FEAT_7_2_EDX,       /* CPUID[EAX=7,ECX=2].EDX */
      FEAT_24_0_EBX,      /* CPUID[EAX=0x24,ECX=0].EBX */
+    FEAT_RDT_15_0_EBX,  /* CPUID[EAX=0xf,ECX=0].EBX (RDT CMT/MBM) */
      FEAT_RDT_15_0_EDX,  /* CPUID[EAX=0xf,ECX=0].EDX (RDT CMT/MBM) */
+    FEAT_RDT_10_0_EBX,  /* CPUID[EAX=0x10,ECX=0].EBX (RDT CAT/MBA) */
      FEATURE_WORDS,
  } FeatureWord;


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