[PATCH v2 18/19] hw/mips/bootloader: Propagate CPU env to bootcpu_supports_isa()

[Philippe Mathieu-Daudé]

Propagate the target specific CPU env to the locally
declared bootcpu_supports_isa() function.

Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
---
 hw/mips/bootloader.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/hw/mips/bootloader.c b/hw/mips/bootloader.c
index a54af8160ef..f02e5aabe48 100644
--- a/hw/mips/bootloader.c
+++ b/hw/mips/bootloader.c
@@ -49,7 +49,7 @@ typedef enum bl_reg {
     BL_REG_RA = 31,
 } bl_reg;
 
-static bool bootcpu_supports_isa(uint64_t isa_mask)
+static bool bootcpu_supports_isa(const CPUMIPSState *env, uint64_t isa_mask)
 {
     return cpu_supports_isa(&MIPS_CPU(first_cpu)->env, isa_mask);
 }
@@ -69,7 +69,7 @@ static void st_nm32_p(void **ptr, uint32_t insn)
 /* Base types */
 static void bl_gen_nop(const CPUMIPSState *env, void **ptr)
 {
-    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+    if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) {
         st_nm32_p(ptr, 0x8000c000);
     } else {
         uint32_t *p = *ptr;
@@ -121,7 +121,7 @@ static void bl_gen_i_type(void **ptr, uint8_t opcode,
 static void bl_gen_dsll(const CPUMIPSState *env, void **p,
                         bl_reg rd, bl_reg rt, uint8_t sa)
 {
-    if (bootcpu_supports_isa(ISA_MIPS3)) {
+    if (bootcpu_supports_isa(env, ISA_MIPS3)) {
         bl_gen_r_type(p, 0, 0, rt, rd, sa, 0x38);
     } else {
         g_assert_not_reached(); /* unsupported */
@@ -130,7 +130,7 @@ static void bl_gen_dsll(const CPUMIPSState *env, void **p,
 
 static void bl_gen_jalr(const CPUMIPSState *env, void **p, bl_reg rs)
 {
-    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+    if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) {
         uint32_t insn = 0;
 
         insn = deposit32(insn, 26, 6, 0b010010); /* JALRC */
@@ -198,7 +198,7 @@ static void bl_gen_sw_nm(void **ptr, bl_reg rt, uint8_t rs, 
uint16_t ofs12)
 static void bl_gen_sw(const CPUMIPSState *env, void **p,
                       bl_reg rt, uint8_t base, uint16_t offset)
 {
-    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+    if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) {
         bl_gen_sw_nm(p, rt, base, offset);
     } else {
         bl_gen_i_type(p, 0x2b, base, rt, offset);
@@ -208,7 +208,7 @@ static void bl_gen_sw(const CPUMIPSState *env, void **p,
 static void bl_gen_sd(const CPUMIPSState *env, void **p,
                       bl_reg rt, uint8_t base, uint16_t offset)
 {
-    if (bootcpu_supports_isa(ISA_MIPS3)) {
+    if (bootcpu_supports_isa(env, ISA_MIPS3)) {
         bl_gen_i_type(p, 0x3f, base, rt, offset);
     } else {
         g_assert_not_reached(); /* unsupported */
@@ -219,7 +219,7 @@ static void bl_gen_sd(const CPUMIPSState *env, void **p,
 static void bl_gen_li(const CPUMIPSState *env, void **p,
                       bl_reg rt, uint32_t imm)
 {
-    if (bootcpu_supports_isa(ISA_NANOMIPS32)) {
+    if (bootcpu_supports_isa(env, ISA_NANOMIPS32)) {
         bl_gen_lui_nm(p, rt, extract32(imm, 12, 20));
         bl_gen_ori_nm(p, rt, rt, extract32(imm, 0, 12));
     } else {
@@ -241,7 +241,7 @@ static void bl_gen_dli(const CPUMIPSState *env, void **p,
 static void bl_gen_load_ulong(const CPUMIPSState *env, void **p,
                               bl_reg rt, target_ulong imm)
 {
-    if (bootcpu_supports_isa(ISA_MIPS3)) {
+    if (bootcpu_supports_isa(env, ISA_MIPS3)) {
         bl_gen_dli(env, p, rt, imm); /* 64bit */
     } else {
         bl_gen_li(env, p, rt, imm); /* 32bit */
@@ -294,7 +294,7 @@ void bl_gen_write_ulong(const MIPSCPU *cpu, void **p,
 
     bl_gen_load_ulong(env, p, BL_REG_K0, val);
     bl_gen_load_ulong(env, p, BL_REG_K1, addr);
-    if (bootcpu_supports_isa(ISA_MIPS3)) {
+    if (bootcpu_supports_isa(env, ISA_MIPS3)) {
         bl_gen_sd(env, p, BL_REG_K0, BL_REG_K1, 0x0);
     } else {
         bl_gen_sw(env, p, BL_REG_K0, BL_REG_K1, 0x0);
-- 
2.47.1