On 1/14/25 6:20 AM, Evgenii Prokopiev wrote:
A behavior of misa.v must be similar as misa.f. So when this bit's field is turned off, mstatus.vs must be turned off too. It follows from the privileged manual of RISC-V, paragraph 3.1.1. "Machine ISA (misa) Register". Signed-off-by: Evgenii Prokopiev <evgenii.prokop...@syntacore.com> ---
Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>
target/riscv/csr.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index eab8e50012..fca2b1b40f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1537,6 +1537,10 @@ static RISCVException write_misa(CPURISCVState *env, int csrno, env->mstatus &= ~MSTATUS_FS; }+ if (!(env->misa_ext & RVV)) {+ env->mstatus &= ~MSTATUS_VS; + } + /* flush translation cache */ tb_flush(env_cpu(env)); env->xl = riscv_cpu_mxl(env);
