On Tue, 2025-01-21 at 15:04 +0800, Jamin Lin wrote: > The INTC0 controller supports GICINT128 to GICINT136, mapping 1:1 to > input and > output IRQs 0 to 8. Previously, the formula "address & 0x0f00" was > used to > derive the IRQ index numbers. > > However, the INTC0 controller also supports GICINT192_201, mapping 1 > input IRQ > pin to 10 output IRQ pins. The pin numbers for input and output are > different. > Additionally, the INTC0 controller supports routing to GIC, SSP, TSP, > and > BOOTMCU, making it difficult to use a formula to determine the index > number of > INTC0 model supported input and output IRQs.
It's also a bit difficult to follow, even having looked at the datasheet. Do you mind adding some documentation with discussion and a diagram of the components involved and the potential interrupt paths? Further, it would be great if the documentation also described the motivation for the interrupt chaining involving involving INT128-159, INTM*, and GICINT192_201, GICINT208 and GICINT224. Clearly it's a thing, but, why? Andrew
