The following changes since commit e8a01102936286e012ed0f00bd7f3b7474d415c9:
Merge tag 'ui-pull-request' of https://gitlab.com/marcandre.lureau/qemu into staging (2025-03-05 21:58:23 +0800) are available in the Git repository at: https://github.com/philmd/qemu.git tags/accel-cpus-20250306 for you to fetch changes up to 92941c94e7f4858fdd61b4c1b85f6d1c6f164359: include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition (2025-03-06 15:46:18 +0100) ---------------------------------------------------------------- Generic CPUs / accelerators patch queue - Merge "qemu/clang-tsa.h" within "qemu/compiler.h" - Various cleanups around accelerators initialization code (better user/system split) - Various trivial cleanups in accel/tcg/, Guard few TCG calls with tcg_enabled() - Explicit disassemble_info endianness - Improve dual-endianness support for MicroBlaze Ignored checkpatch error: WARNING: architecture specific defines should be avoided #215: FILE: include/qemu/compiler.h:215: +#ifdef __clang__ ---------------------------------------------------------------- Denis Rastyogin (1): target/mips: Fix possible MSA int overflow Phil Dennis-Jordan (1): target/i386/hvf: Variable type fixup in decoder Philippe Mathieu-Daudé (52): qemu/compiler: Absorb 'clang-tsa.h' gdbstub: Clarify no more than @gdb_num_core_regs can be accessed gdbstub: Check for TCG before calling tb_flush() cpus: Cache CPUClass early in instance_init() handler cpus: Keep default fields initialization in cpu_common_initfn() accel/accel: Make TYPE_ACCEL abstract accel/tcg: Remove pointless initialization of cflags_next_tb accel/tcg: Build tcg_flags helpers as common code accel/tcg: Restrict tlb_init() / destroy() to TCG accel/tcg: Restrict 'icount_align_option' global to TCG accel/tcg: Rename 'hw/core/tcg-cpu-ops.h' -> 'accel/tcg/cpu-ops.h' accel: Rename 'hw/core/accel-cpu.h' -> 'accel/accel-cpu-target.h' accel: Forward-declare AccelOpsClass in 'qemu/typedefs.h' accel/accel-cpu-target.h: Include missing 'cpu.h' header accel/tcg: Include missing bswap headers in user-exec.c accel/tcg: Take mmap lock in the whole cpu_memory_rw_debug() function accel/tcg: Avoid using lock_user() in cpu_memory_rw_debug() accel/tcg: Move cpu_memory_rw_debug() user implementation to user-exec.c accel/kvm: Remove unused 'system/cpus.h' header in kvm-cpus.h cpus: Fix style in cpu-target.c cpus: Restrict cpu_common_post_load() code to TCG cpus: Have cpu_class_init_props() per user / system emulation cpus: Have cpu_exec_initfn() per user / system emulation cpus: Restrict cpu_get_memory_mapping() to system emulation hw/core/generic-loader: Do not open-code cpu_set_pc() target/microblaze: Explode MO_TExx -> MO_TE | MO_xx target/microblaze: Set MO_TE once in do_load() / do_store() target/microblaze: Introduce mo_endian() helper target/microblaze: Consider endianness while translating code target/openrisc: Call cpu_openrisc_clock_init() in cpu_realize() target/hexagon: Ensure not being build on system emulation target/rx: Ensure not being build on user emulation target/tricore: Ensure not being build on user emulation target: Set disassemble_info::endian value for little-endian targets target: Set disassemble_info::endian value for big-endian targets target/arm: Set disassemble_info::endian value in disas_set_info() target/microblaze: Set disassemble_info::endian value in disas_set_info target/mips: Set disassemble_info::endian value in disas_set_info() target/ppc: Set disassemble_info::endian value in disas_set_info() target/riscv: Set disassemble_info::endian value in disas_set_info() target/sh4: Set disassemble_info::endian value in disas_set_info() target/xtensa: Set disassemble_info::endian value in disas_set_info() disas: Remove target_words_bigendian() call in initialize_debug_target() target/i386: Constify X86CPUModel uses target/sparc: Constify SPARCCPUClass::cpu_def target/xtensa: Finalize config in xtensa_register_core() target/riscv: Declare RISCVCPUClass::misa_mxl_max as RISCVMXL target/riscv: Convert misa_mxl_max using GLib macros target/alpha: Do not mix exception flags and FPCR bits target/i386: Mark WHPX APIC region as little-endian system: Open-code qemu_init_arch_modules() using target_name() include: Poison TARGET_PHYS_ADDR_SPACE_BITS definition MAINTAINERS | 5 +- accel/kvm/kvm-cpus.h | 2 - accel/tcg/internal-common.h | 13 ++ bsd-user/qemu.h | 1 - .../accel-cpu.h => accel/accel-cpu-target.h} | 7 +- .../tcg-cpu-ops.h => accel/tcg/cpu-ops.h} | 0 include/block/block_int-common.h | 1 - include/block/graph-lock.h | 2 - include/exec/exec-all.h | 16 -- include/exec/page-protection.h | 2 - include/exec/poison.h | 1 + include/hw/core/cpu.h | 6 +- include/qemu/clang-tsa.h | 114 ---------- include/qemu/compiler.h | 96 ++++++++ include/qemu/thread.h | 1 - include/qemu/typedefs.h | 1 + include/system/accel-ops.h | 1 - include/system/arch_init.h | 2 - include/system/cpus.h | 4 - target/hexagon/cpu.h | 4 + target/i386/cpu.h | 2 +- target/microblaze/cpu.h | 7 + target/riscv/cpu.h | 2 +- target/rx/cpu.h | 6 +- target/sparc/cpu.h | 2 +- target/tricore/cpu.h | 4 + target/xtensa/cpu.h | 2 +- accel/accel-system.c | 1 + accel/accel-target.c | 3 +- accel/hvf/hvf-accel-ops.c | 1 + accel/kvm/kvm-accel-ops.c | 1 + accel/qtest/qtest.c | 1 + accel/stubs/tcg-stub.c | 4 - accel/tcg/cpu-exec-common.c | 34 ++- accel/tcg/cpu-exec.c | 35 +-- accel/tcg/cputlb.c | 2 +- accel/tcg/icount-common.c | 2 + accel/tcg/monitor.c | 1 - accel/tcg/tcg-accel-ops.c | 1 + accel/tcg/translate-all.c | 3 +- accel/tcg/user-exec-stub.c | 11 + accel/tcg/user-exec.c | 84 ++++++- accel/tcg/watchpoint.c | 2 +- accel/xen/xen-all.c | 1 + block/create.c | 1 - bsd-user/signal.c | 2 +- cpu-common.c | 1 - cpu-target.c | 205 ++---------------- disas/disas-common.c | 8 +- gdbstub/system.c | 6 +- hw/core/cpu-common.c | 6 +- hw/core/cpu-system.c | 47 ++++ hw/core/cpu-user.c | 32 +++ hw/core/generic-loader.c | 5 +- hw/mips/jazz.c | 2 +- hw/openrisc/openrisc_sim.c | 2 - hw/openrisc/virt.c | 2 - linux-user/signal.c | 2 +- system/arch_init.c | 9 - system/cpus.c | 1 + system/globals.c | 1 - system/physmem.c | 2 +- system/vl.c | 7 +- target/alpha/cpu.c | 3 +- target/alpha/fpu_helper.c | 15 +- target/arm/cpu.c | 12 +- target/arm/tcg/cpu-v7m.c | 2 +- target/arm/tcg/cpu32.c | 2 +- target/arm/tcg/mte_helper.c | 2 +- target/arm/tcg/sve_helper.c | 2 +- target/avr/cpu.c | 3 +- target/avr/helper.c | 2 +- target/hexagon/cpu.c | 3 +- target/hppa/cpu.c | 3 +- target/i386/cpu.c | 9 +- target/i386/hvf/hvf-cpu.c | 2 +- target/i386/hvf/x86_decode.c | 4 +- target/i386/kvm/kvm-cpu.c | 2 +- target/i386/nvmm/nvmm-accel-ops.c | 1 + target/i386/tcg/tcg-cpu.c | 4 +- target/i386/whpx/whpx-accel-ops.c | 1 + target/i386/whpx/whpx-apic.c | 2 +- target/loongarch/cpu.c | 3 +- target/m68k/cpu.c | 3 +- target/microblaze/cpu.c | 4 +- target/microblaze/gdbstub.c | 5 - target/microblaze/translate.c | 49 +++-- target/mips/cpu.c | 12 +- target/mips/tcg/msa_helper.c | 6 +- target/openrisc/cpu.c | 7 +- target/openrisc/gdbstub.c | 5 - target/ppc/cpu_init.c | 4 +- target/ppc/kvm.c | 2 +- target/riscv/cpu.c | 19 +- target/riscv/cpu_helper.c | 2 +- target/riscv/kvm/kvm-cpu.c | 2 +- target/riscv/tcg/tcg-cpu.c | 4 +- target/rx/cpu.c | 9 +- target/rx/helper.c | 4 - target/s390x/cpu.c | 3 +- target/s390x/tcg/mem_helper.c | 2 +- target/sh4/cpu.c | 4 +- target/sparc/cpu.c | 3 +- target/tricore/cpu.c | 2 +- target/xtensa/cpu.c | 4 +- target/xtensa/helper.c | 5 +- tests/unit/test-bdrv-drain.c | 1 - tests/unit/test-block-iothread.c | 1 - util/qemu-thread-posix.c | 1 - hw/core/meson.build | 5 +- 110 files changed, 544 insertions(+), 533 deletions(-) rename include/{hw/core/accel-cpu.h => accel/accel-cpu-target.h} (92%) rename include/{hw/core/tcg-cpu-ops.h => accel/tcg/cpu-ops.h} (100%) delete mode 100644 include/qemu/clang-tsa.h create mode 100644 hw/core/cpu-user.c -- 2.47.1
