The following changes since commit d9a4282c4b690e45d25c2b933f318bb41eeb271d:
Merge tag 'pull-tcg-20250308' of https://gitlab.com/rth7680/qemu into staging (2025-03-09 11:45:00 +0800) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-aspeed-20250309 for you to fetch changes up to 5ab179db11ca297c9e89a6d57f954d31965cbd7b: docs/specs: Add aspeed-intc (2025-03-09 14:36:53 +0100) ---------------------------------------------------------------- aspeed queue: * Updated Aspeed OpenBMC functional test images * Introduced functional tests for witherspoon and bletchley machines * Added support for Non-maskable Interrupt on AST2700 SoC * Fixed HW strapping on AST2700 SoC * Added AST2700 HACE support * Added AST2700 A1 SoC support * Intoduced new ast2700a1-evb machine ---------------------------------------------------------------- Cédric Le Goater (6): tests/functional: Introduce a new test routine for OpenBMC images tests/functional: Update OpenBMC image of palmetto machine tests/functional: Update OpenBMC image of romulus machine tests/functional: Introduce a witherspoon machine test tests/functional: Introduce a bletchley machine test aspeed: Remove duplicate typename in AspeedSoCClass Jamin Lin (40): aspeed/soc: Support Non-maskable Interrupt for AST2700 hw/misc/aspeed_hace: Fix coding style hw/misc/aspeed_hace: Add AST2700 support hw/arm/aspeed_ast27x0: Add HACE support for AST2700 hw/misc/aspeed_hace: Fix boot issue in the Crypto Manager Self Test hw/misc/aspeed_scu: Skipping dram_init in u-boot hw/misc/aspeed_scu: Fix the revision ID cannot be set in the SOC layer for AST2700 hw/arm/aspeed Update HW Strap Default Values for AST2700 hw/misc/aspeed_scu: Fix the hw-strap1 cannot be set in the SOC layer for AST2700 hw/arm/aspeed_ast27x0.c Separate HW Strap Registers for SCU and SCUIO hw/arm/aspeed_ast27x0.c Fix boot issue for AST2700 hw/intc/aspeed: Support setting different memory size hw/intc/aspeed: Rename status_addr and addr to status_reg and reg for clarity hw/intc/aspeed: Introduce dynamic allocation for regs array hw/intc/aspeed: Support setting different register size hw/intc/aspeed: Reduce regs array size by adding a register sub-region hw/intc/aspeed: Introduce helper functions for enable and status registers hw/intc/aspeed: Add object type name to trace events for better debugging hw/arm/aspeed: Rename IRQ table and machine name for AST2700 A0 hw/arm/aspeed_ast27x0: Sort the IRQ table by IRQ number hw/intc/aspeed: Support different memory region ops hw/intc/aspeed: Rename num_ints to num_inpins for clarity hw/intc/aspeed: Add support for multiple output pins in INTC hw/intc/aspeed: Refactor INTC to support separate input and output pin indices hw/intc/aspeed: Introduce AspeedINTCIRQ structure to save the irq index and register address hw/intc/aspeed: Introduce IRQ handler function to reduce code duplication hw/intc/aspeed: Add Support for Multi-Output IRQ Handling hw/intc/aspeed: Add Support for AST2700 INTCIO Controller hw/misc/aspeed_scu: Add Support for AST2700/AST2750 A1 Silicon Revisions hw/arm/aspeed_ast27x0.c Support AST2700 A1 GIC Interrupt Mapping hw/arm/aspeed_ast27x0: Define an Array of AspeedINTCState with Two Instances hw/arm/aspeed_ast27x0: Support two levels of INTC controllers for AST2700 A1 hw/arm/aspeed_ast27x0: Add SoC Support for AST2700 A1 hw/arm/aspeed: Add Machine Support for AST2700 A1 hw/arm/aspeed_ast27x0: Sort the memmap table by mapping address tests/functional/aspeed: Introduce start_ast2700_test API tests/functional/aspeed: Update temperature hwmon path tests/functional/aspeed: Update test ASPEED SDK v09.05 tests/functional/aspeed: Add test case for AST2700 A1 docs/specs: Add aspeed-intc docs/specs/aspeed-intc.rst | 136 +++++ docs/specs/index.rst | 1 + include/hw/arm/aspeed_soc.h | 4 +- include/hw/intc/aspeed_intc.h | 36 +- include/hw/misc/aspeed_hace.h | 2 + include/hw/misc/aspeed_scu.h | 2 + hw/arm/aspeed.c | 39 +- hw/arm/aspeed_ast10x0.c | 3 +- hw/arm/aspeed_ast2400.c | 4 +- hw/arm/aspeed_ast2600.c | 3 +- hw/arm/aspeed_ast27x0.c | 359 +++++++++---- hw/intc/aspeed_intc.c | 667 ++++++++++++++++++------ hw/misc/aspeed_hace.c | 55 +- hw/misc/aspeed_scu.c | 10 +- hw/intc/trace-events | 25 +- tests/functional/aspeed.py | 24 +- tests/functional/meson.build | 4 + tests/functional/test_aarch64_aspeed.py | 47 +- tests/functional/test_arm_aspeed_bletchley.py | 25 + tests/functional/test_arm_aspeed_palmetto.py | 13 +- tests/functional/test_arm_aspeed_romulus.py | 13 +- tests/functional/test_arm_aspeed_witherspoon.py | 25 + 22 files changed, 1150 insertions(+), 347 deletions(-) create mode 100644 docs/specs/aspeed-intc.rst create mode 100644 tests/functional/test_arm_aspeed_bletchley.py create mode 100644 tests/functional/test_arm_aspeed_witherspoon.py
