On Thu, Mar 6, 2025 at 4:33 PM Michael Tokarev <m...@tls.msk.ru> wrote: > > 21.01.2025 20:06, Daniel Henrique Barboza wrote: > > Hi, > > > > In this new version, in patch 2, we're using the address 'size' val from > > riscv_cpu_tlb_fill() instead of infering it from the CPU XLEN. > > > > No other changes made. Patches based on master. > > > > Changes from v2: > > - patch 2: > > - use 'size' instead of infering wp_len using the CPU XLEN > > - v2 link: > > https://lore.kernel.org/qemu-riscv/20250120204910.1317013-1-dbarb...@ventanamicro.com/ > > > > Daniel Henrique Barboza (2): > > target/riscv/debug.c: use wp size = 4 for 32-bit CPUs > > target/riscv: throw debug exception before page fault > > Hi! > > Is this a qemu-stable material?
Yes > > If yes, is it worth to pick it up for older stable series > (currently active series are 7.2 and 8.2)? If it applies then it probably is > > Please keep Cc: qemu-stable@ for fixes which should be picked up > for the stable series. Sorry, I always forget :( Alistair > > Thanks, > > /mjt >
