From: Santiago Monserrat Campanello <santimons...@gmail.com> semihosting link to risc-v changed
Signed-off-by: Santiago Monserrat Campanello <santimons...@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2717 Reviewed-by: Alistair Francis <alistair.fran...@wdc.com> Reviewed-by: Thomas Huth <th...@redhat.com> Message-ID: <20250305102632.91376-1-santimons...@gmail.com> Signed-off-by: Alistair Francis <alistair.fran...@wdc.com> (cherry picked from commit 672cb29d1e811180bf1aeefbcb0936ecd5bd3853) Signed-off-by: Michael Tokarev <m...@tls.msk.ru> diff --git a/docs/about/emulation.rst b/docs/about/emulation.rst index 3028d5fff7..951f5ae1c4 100644 --- a/docs/about/emulation.rst +++ b/docs/about/emulation.rst @@ -171,7 +171,7 @@ for that architecture. - Unified Hosting Interface (MD01069) * - RISC-V - System and User-mode - - https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc + - https://github.com/riscv-non-isa/riscv-semihosting/blob/main/riscv-semihosting.adoc * - Xtensa - System - Tensilica ISS SIMCALL -- 2.39.5
