> -----Original Message-----
> From: Sid Manning <sidn...@quicinc.com>
> Sent: Thursday, March 20, 2025 3:26 PM
> To: ltaylorsimp...@gmail.com; 'Brian Cain'
> <brian.c...@oss.qualcomm.com>; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org; Matheus Bernardino
> (QUIC) <quic_mathb...@quicinc.com>; a...@rev.ng; a...@rev.ng; Marco
> Liebel (QUIC) <quic_mlie...@quicinc.com>; alex.ben...@linaro.org; Mark
> Burton (QUIC) <quic_mbur...@quicinc.com>; Brian Cain
> <bc...@quicinc.com>
> Subject: RE: [PATCH 22/39] target/hexagon: Implement setprio, resched
> > > + if (lowest_th_prio > best_prio) {
> > > + qemu_log_mask(CPU_LOG_INT,
> > > + "%s: raising resched int %d, cur PC 0x" TARGET_FMT_lx
> > > "\n",
> > > + __func__, int_number, arch_get_thread_reg(env,
> > HEX_REG_PC));
> > > + SET_SYSTEM_FIELD(env, HEX_SREG_BESTWAIT, BESTWAIT_PRIO,
> > > 0x1ff);
> >
> > What is the significance of 0x1ff? The field is 10 bits, so this
> > isn't setting all the bits.
> > Should this be lowest_th_prio?
> [Sid Manning]
>
> Hi Taylor,
>
> The value 0x1ff is correct but it does look like BESTWAIT_PRIO is not, it
> should
> be 9 not 10 target/hexagon/reg_fields_def.h.inc
>
> It looks like it was added in "PATCH 19/38 target/hexagon: Define register
> fields for system regs"
> I will make a fixup to that patch and correct the value.
I see.
If the intent is to set all the bits in the field, then use ~0.
Taylor
