On Tue, Mar 18, 2025 at 02:07:54PM +0100, Corvin Köhne wrote:
> From: YannickV <y.vos...@beckhoff.com>
>
> A DMA transfer to destination address `0xffffffff` should trigger a
> bitstream load via the PCAP interface. Currently, this case is not
> intercepted, causing loaders to enter an infinite loop when polling
> the status register.
>
> This commit adds a check for `0xffffffff` as the destination address.
> If detected, the relevant status register bits (`DMA_DONE`,
> `DMA_P_DONE`, and `PCFG_DONE`) are set to indicate a successful
> bitstream load. If the address is different, the DMA transfer proceeds
> as usual. A successful load is indicated but nothing is actually
> done. Guests relying on FPGA functions are still known to fail.
>
> This feature is required for the integration of the Beckhoff
> CX7200 model.
Thanks, LGTM:
Reviewed-by: Edgar E. Iglesias <edgar.igles...@amd.com>
>
> Signed-off-by: Yannick Voßen <y.vos...@beckhoff.com>
> ---
> hw/dma/xlnx-zynq-devcfg.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c
> index 0fd0d23f57..b838c1c0d0 100644
> --- a/hw/dma/xlnx-zynq-devcfg.c
> +++ b/hw/dma/xlnx-zynq-devcfg.c
> @@ -247,7 +247,14 @@ static uint64_t r_lock_pre_write(RegisterInfo *reg,
> uint64_t val)
> static void r_dma_dst_len_post_write(RegisterInfo *reg, uint64_t val)
> {
> XlnxZynqDevcfg *s = XLNX_ZYNQ_DEVCFG(reg->opaque);
> -
> + if ((s->regs[R_DMA_DST_ADDR]) == 0xffffffff) {
> + DB_PRINT("bitstream loading detected\n");
> + s->regs[R_INT_STS] |= R_INT_STS_DMA_DONE_MASK |
> + R_INT_STS_DMA_P_DONE_MASK |
> + R_INT_STS_PCFG_DONE_MASK;
> + xlnx_zynq_devcfg_update_ixr(s);
> + return;
> + }
> s->dma_cmd_fifo[s->dma_cmd_fifo_num] = (XlnxZynqDevcfgDMACmd) {
> .src_addr = s->regs[R_DMA_SRC_ADDR] & ~0x3UL,
> .dest_addr = s->regs[R_DMA_DST_ADDR] & ~0x3UL,
> --
> 2.49.0
>
