This is an alternate, but less exact approach. It assumes that there will never be a 16 or 48-bit csr write instruction. This feels dirtier, but it's a fair assumption involves much less faff.
r~ Richard Henderson (2): target/riscv: Update pc before csrw, csrrw target/riscv: Fix write_misa vs aligned next_pc target/riscv/csr.c | 9 ++++++--- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++++ 2 files changed, 10 insertions(+), 3 deletions(-) -- 2.43.0
