On Sat, Apr 26, 2025 at 1:23 AM Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.hender...@linaro.org>
Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>
Alistair
> ---
> target/riscv/cpu.h | 4 ++--
> target/riscv/csr.c | 8 ++++----
> target/riscv/op_helper.c | 9 +++++----
> 3 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 2c0524d0be..8b84793b15 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -851,8 +851,8 @@ typedef RISCVException (*riscv_csr_op_fn)(CPURISCVState
> *env, int csrno,
> RISCVException riscv_csrr_i128(CPURISCVState *env, int csrno,
> Int128 *ret_value);
> RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
> - Int128 *ret_value,
> - Int128 new_value, Int128 write_mask);
> + Int128 *ret_value, Int128 new_value,
> + Int128 write_mask, uintptr_t ra);
>
> typedef RISCVException (*riscv_csr_read128_fn)(CPURISCVState *env, int csrno,
> Int128 *ret_value);
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index 097640e25d..a663f527a4 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -5656,8 +5656,8 @@ RISCVException riscv_csrr_i128(CPURISCVState *env, int
> csrno,
> }
>
> RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
> - Int128 *ret_value,
> - Int128 new_value, Int128 write_mask)
> + Int128 *ret_value, Int128 new_value,
> + Int128 write_mask, uintptr_t ra)
> {
> RISCVException ret;
>
> @@ -5668,7 +5668,7 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int
> csrno,
>
> if (csr_ops[csrno].read128) {
> return riscv_csrrw_do128(env, csrno, ret_value,
> - new_value, write_mask, 0);
> + new_value, write_mask, ra);
> }
>
> /*
> @@ -5681,7 +5681,7 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int
> csrno,
> target_ulong old_value;
> ret = riscv_csrrw_do64(env, csrno, &old_value,
> int128_getlo(new_value),
> - int128_getlo(write_mask), 0);
> + int128_getlo(write_mask), ra);
> if (ret == RISCV_EXCP_NONE && ret_value) {
> *ret_value = int128_make64(old_value);
> }
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index aee16e2e3a..e3770a2655 100644
> --- a/target/riscv/op_helper.c
> +++ b/target/riscv/op_helper.c
> @@ -108,7 +108,7 @@ void helper_csrw_i128(CPURISCVState *env, int csr,
> {
> RISCVException ret = riscv_csrrw_i128(env, csr, NULL,
> int128_make128(srcl, srch),
> - UINT128_MAX);
> + UINT128_MAX, GETPC());
>
> if (ret != RISCV_EXCP_NONE) {
> riscv_raise_exception(env, ret, GETPC());
> @@ -116,13 +116,14 @@ void helper_csrw_i128(CPURISCVState *env, int csr,
> }
>
> target_ulong helper_csrrw_i128(CPURISCVState *env, int csr,
> - target_ulong srcl, target_ulong srch,
> - target_ulong maskl, target_ulong maskh)
> + target_ulong srcl, target_ulong srch,
> + target_ulong maskl, target_ulong maskh)
> {
> Int128 rv = int128_zero();
> RISCVException ret = riscv_csrrw_i128(env, csr, &rv,
> int128_make128(srcl, srch),
> - int128_make128(maskl, maskh));
> + int128_make128(maskl, maskh),
> + GETPC());
>
> if (ret != RISCV_EXCP_NONE) {
> riscv_raise_exception(env, ret, GETPC());
> --
> 2.43.0
>
>
