On Wed, 30 Apr 2025 at 02:41, Daniel Henrique Barboza
<dbarb...@ventanamicro.com> wrote:
>
>
>
> On 4/29/25 9:40 AM, Daniel Henrique Barboza wrote:
> > Joel,
> >
> > I'll make these changes in this patch to be consistent with what we've
> > been discussing:
> >
> > - change addr to hwaddr
> > - use HWADDR_PRIx instead of PRIx64
> >
> > i.e. this diff:
> >
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > index 1eae84db15..0020d8f404 100644
> > --- a/hw/riscv/virt.c
> > +++ b/hw/riscv/virt.c
> > @@ -303,12 +303,13 @@ static void create_fdt_socket_cpus(RISCVVirtState *s,
> > int socket,
> > static void create_fdt_socket_memory(RISCVVirtState *s, int socket)
> > {
> > g_autofree char *mem_name = NULL;
> > - uint64_t addr, size;
> > + hwaddr addr;
> > + uint64_t size;
Size should be a hwaddr too. This would be consistent with how
MemMapEntry describes the base/size pairs.
> > MachineState *ms = MACHINE(s);
> >
> > addr = s->memmap[VIRT_DRAM].base + riscv_socket_mem_offset(ms,
> > socket);
> > size = riscv_socket_mem_size(ms, socket);
> > - mem_name = g_strdup_printf("/memory@%"PRIx64, addr);
> > + mem_name = g_strdup_printf("/memory@%"HWADDR_PRIx, addr);
> > qemu_fdt_add_subnode(ms->fdt, mem_name);
> > qemu_fdt_setprop_cells(ms->fdt, mem_name, "reg",
> > addr >> 32, addr, size >> 32, size);
> >
> >
> > I did this change and applied your "hw/riscv/virt: device tree reg
> > cleanups" series on top
> > of it, and there are no conflicts. No change needed in your side.
>
> It seems I was wrong. The v2 will conflict with your patch 03. I think a
> rebase from
> your series can't be avoided ...
If you want to pick them up as part of your series, and send them as a
big patch set then that's fine with me.
Otherwise I'll wait until we've got yours staged and send a new version out.
Thanks!
Joel
