Re: [PATCH 7/7] target/riscv: Fix write_misa vs aligned next_pc

[Alistair Francis]

On Wed, Apr 30, 2025 at 12:34 AM Richard Henderson
<richard.hender...@linaro.org> wrote:
>
> On 4/25/25 08:23, Richard Henderson wrote:
> > -    if ((val & RVC) && (GETPC() & ~3) != 0) {
> > +    /* Suppress 'C' if next instruction is not aligned. */
> > +    if ((val & RVC) && (get_next_pc(env, ra) & ~3) != 0) {
>
> Bah.  I preserved a second bug here: not "& ~3" but "& 3".

Good catch

I squashed this fix into the patch

Alistair

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> r~
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