On Tue, Apr 29, 2025 at 10:46 PM Daniel Henrique Barboza <dbarb...@ventanamicro.com> wrote: > > Hi, > > This version has a fix on patch 8 where I did use an extra variable and > happened to set the wrong mask too. > > We'll let the compiler cast the uint32_t from an uint64_t reg. A cast > was added for extra clarity when reading the code, although some picky > toolchains might require an explicit cast in this case too. > > No other changes made. > > Patches missing acks/reviews: patch 8. > > Changes from v4: > - patch 8: > - remove the 'reg32' variable and add an uint32_t cast when passing > the uint64_t var 'reg' to kvm_cpu_csr_set_u32() > - v4 link: > https://lore.kernel.org/qemu-riscv/20250428192323.84992-1-dbarb...@ventanamicro.com/ > > Daniel Henrique Barboza (9): > target/riscv/kvm: minor fixes/tweaks > target/riscv/kvm: fix leak in kvm_riscv_init_multiext_cfg() > target/riscv/kvm: turn u32/u64 reg functions into macros > target/riscv/kvm: turn kvm_riscv_reg_id_ulong() into a macro > target/riscv/kvm: add kvm_csr_cfgs[] > target/riscv/kvm: do not read unavailable CSRs > target/riscv/kvm: add senvcfg CSR > target/riscv/kvm: read/write KVM regs via env size > target/riscv/kvm: add scounteren CSR
Thanks! Applied to riscv-to-apply.next Alistair > > target/riscv/cpu.h | 1 + > target/riscv/kvm/kvm-cpu.c | 333 +++++++++++++++++++++++-------------- > 2 files changed, 212 insertions(+), 122 deletions(-) > > -- > 2.49.0 > >
