Suggested-by: Thomas Huth <th...@redhat.com> Signed-off-by: Michael Tokarev <m...@tls.msk.ru> --- qapi/qom.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/qapi/qom.json b/qapi/qom.json index 28ce24cd8d..04c118e4d6 100644 --- a/qapi/qom.json +++ b/qapi/qom.json @@ -871,7 +871,7 @@ # link characteristics read from PCIe Configuration space. # To get the full path latency from CPU to CXL attached DRAM # CXL device: Add the latency from CPU to Generic Port (from -# HMAT indexed via the the node ID in this SRAT structure) to +# HMAT indexed via the node ID in this SRAT structure) to # that for CXL bus links, the latency across intermediate switches # and from the EP port to the actual memory. Bandwidth is more # complex as there may be interleaving across multiple devices -- 2.39.5
