Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouv...@linaro.org>
---
target/arm/cpu.h | 54 +-----------------------------
target/arm/cpu_has_feature.h | 65 ++++++++++++++++++++++++++++++++++++
2 files changed, 66 insertions(+), 53 deletions(-)
create mode 100644 target/arm/cpu_has_feature.h
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 116745975fa..cf3ff21965c 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -30,6 +30,7 @@
#include "exec/gdbstub.h"
#include "exec/page-protection.h"
#include "qapi/qapi-types-common.h"
+#include "target/arm/cpu_has_feature.h"
#include "target/arm/gtimer.h"
#define EXCP_UDEF 1 /* undefined instruction */
@@ -2376,59 +2377,6 @@ FIELD(MFAR, NS, 63, 1)
QEMU_BUILD_BUG_ON(ARRAY_SIZE(((ARMCPU *)0)->ccsidr) <=
R_V7M_CSSELR_INDEX_MASK);
-/* If adding a feature bit which corresponds to a Linux ELF
- * HWCAP bit, remember to update the feature-bit-to-hwcap
- * mapping in linux-user/elfload.c:get_elf_hwcap().
- */
-enum arm_features {
- ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
- ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
- ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
- ARM_FEATURE_V6,
- ARM_FEATURE_V6K,
- ARM_FEATURE_V7,
- ARM_FEATURE_THUMB2,
- ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
- ARM_FEATURE_NEON,
- ARM_FEATURE_M, /* Microcontroller profile. */
- ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
- ARM_FEATURE_THUMB2EE,
- ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
- ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
- ARM_FEATURE_V4T,
- ARM_FEATURE_V5,
- ARM_FEATURE_STRONGARM,
- ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
- ARM_FEATURE_GENERIC_TIMER,
- ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
- ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
- ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
- ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
- ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
- ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
- ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
- ARM_FEATURE_V8,
- ARM_FEATURE_AARCH64, /* supports 64 bit mode */
- ARM_FEATURE_CBAR, /* has cp15 CBAR */
- ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
- ARM_FEATURE_EL2, /* has EL2 Virtualization support */
- ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
- ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
- ARM_FEATURE_PMU, /* has PMU support */
- ARM_FEATURE_VBAR, /* has cp15 VBAR */
- ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
- ARM_FEATURE_M_MAIN, /* M profile Main Extension */
- ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
- /*
- * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
- * if the board doesn't set a value, instead of 1GHz. It is for backwards
- * compatibility and used only with CPU definitions that were already
- * in QEMU before we changed the default. It should not be set on any
- * CPU types added in future.
- */
- ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
-};
-
static inline int arm_feature(CPUARMState *env, int feature)
{
return (env->features & (1ULL << feature)) != 0;
diff --git a/target/arm/cpu_has_feature.h b/target/arm/cpu_has_feature.h
new file mode 100644
index 00000000000..2adfccd9208
--- /dev/null
+++ b/target/arm/cpu_has_feature.h
@@ -0,0 +1,65 @@
+/*
+ * Helper to check ARM CPU has features
+ *
+ * Copyright (c) 2003 Fabrice Bellard
+ *
+ * SPDX-License-Identifier: LGPL-2.1-or-later
+ */
+#ifndef TARGET_ARM_CPU_HAS_FEATURE_H
+#define TARGET_ARM_CPU_HAS_FEATURE_H
+
+/*
+ * If adding a feature bit which corresponds to a Linux ELF
+ * HWCAP bit, remember to update the feature-bit-to-hwcap
+ * mapping in linux-user/elfload.c:get_elf_hwcap().
+ */
+typedef enum arm_features {
+ ARM_FEATURE_AUXCR, /* ARM1026 Auxiliary control register. */
+ ARM_FEATURE_XSCALE, /* Intel XScale extensions. */
+ ARM_FEATURE_IWMMXT, /* Intel iwMMXt extension. */
+ ARM_FEATURE_V6,
+ ARM_FEATURE_V6K,
+ ARM_FEATURE_V7,
+ ARM_FEATURE_THUMB2,
+ ARM_FEATURE_PMSA, /* no MMU; may have Memory Protection Unit */
+ ARM_FEATURE_NEON,
+ ARM_FEATURE_M, /* Microcontroller profile. */
+ ARM_FEATURE_OMAPCP, /* OMAP specific CP15 ops handling. */
+ ARM_FEATURE_THUMB2EE,
+ ARM_FEATURE_V7MP, /* v7 Multiprocessing Extensions */
+ ARM_FEATURE_V7VE, /* v7 Virtualization Extensions (non-EL2 parts) */
+ ARM_FEATURE_V4T,
+ ARM_FEATURE_V5,
+ ARM_FEATURE_STRONGARM,
+ ARM_FEATURE_VAPA, /* cp15 VA to PA lookups */
+ ARM_FEATURE_GENERIC_TIMER,
+ ARM_FEATURE_MVFR, /* Media and VFP Feature Registers 0 and 1 */
+ ARM_FEATURE_DUMMY_C15_REGS, /* RAZ/WI all of cp15 crn=15 */
+ ARM_FEATURE_CACHE_TEST_CLEAN, /* 926/1026 style test-and-clean ops */
+ ARM_FEATURE_CACHE_DIRTY_REG, /* 1136/1176 cache dirty status register */
+ ARM_FEATURE_CACHE_BLOCK_OPS, /* v6 optional cache block operations */
+ ARM_FEATURE_MPIDR, /* has cp15 MPIDR */
+ ARM_FEATURE_LPAE, /* has Large Physical Address Extension */
+ ARM_FEATURE_V8,
+ ARM_FEATURE_AARCH64, /* supports 64 bit mode */
+ ARM_FEATURE_CBAR, /* has cp15 CBAR */
+ ARM_FEATURE_CBAR_RO, /* has cp15 CBAR and it is read-only */
+ ARM_FEATURE_EL2, /* has EL2 Virtualization support */
+ ARM_FEATURE_EL3, /* has EL3 Secure monitor support */
+ ARM_FEATURE_THUMB_DSP, /* DSP insns supported in the Thumb encodings */
+ ARM_FEATURE_PMU, /* has PMU support */
+ ARM_FEATURE_VBAR, /* has cp15 VBAR */
+ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */
+ ARM_FEATURE_M_MAIN, /* M profile Main Extension */
+ ARM_FEATURE_V8_1M, /* M profile extras only in v8.1M and later */
+ /*
+ * ARM_FEATURE_BACKCOMPAT_CNTFRQ makes the CPU default cntfrq be 62.5MHz
+ * if the board doesn't set a value, instead of 1GHz. It is for backwards
+ * compatibility and used only with CPU definitions that were already
+ * in QEMU before we changed the default. It should not be set on any
+ * CPU types added in future.
+ */
+ ARM_FEATURE_BACKCOMPAT_CNTFRQ, /* 62.5MHz timer default */
+} ArmCpuFeature;
+
+#endif
--
2.47.1
