Re: [PATCH 18/50] pnv/xive2: Print value in invalid register write logging

[Mike Kowal]

On 5/11/2025 10:10 PM, Nicholas Piggin wrote:

From: Michael Kowal <ko...@linux.ibm.com>

This can make it easier to see what the target system is trying to
do.

Reviewed-by: Michael Kowal <ko...@linux.ibm.com>

Thanks MAK

[npiggin: split from larger patch]
Signed-off-by: Michael Kowal <ko...@linux.ibm.com>
---
  hw/intc/pnv_xive2.c | 24 ++++++++++++++++--------
  1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index d7ca97ecbb..fcf5b2e75c 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/pnv_xive2.c
@@ -1197,7 +1197,8 @@ static void pnv_xive2_ic_cq_write(void *opaque, hwaddr 
offset,
      case CQ_FIRMASK_OR: /* FIR error reporting */
          break;
      default:
-        xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx, offset);
+        xive2_error(xive, "CQ: invalid write 0x%"HWADDR_PRIx" value 0x%"PRIx64,
+                    offset, val);
          return;
      }

@@ -1495,7 +1496,8 @@ static void pnv_xive2_ic_vc_write(void *opaque, hwaddr offset,

          break;

default:

-        xive2_error(xive, "VC: invalid write @%"HWADDR_PRIx, offset);
+        xive2_error(xive, "VC: invalid write @0x%"HWADDR_PRIx" value 
0x%"PRIx64,
+                    offset, val);
          return;
      }

@@ -1703,7 +1705,8 @@ static void pnv_xive2_ic_pc_write(void *opaque, hwaddr offset,

          break;

default:

-        xive2_error(xive, "PC: invalid write @%"HWADDR_PRIx, offset);
+        xive2_error(xive, "PC: invalid write @0x%"HWADDR_PRIx" value 
0x%"PRIx64,
+                    offset, val);
          return;
      }

@@ -1790,7 +1793,8 @@ static void pnv_xive2_ic_tctxt_write(void *opaque, hwaddr offset,

          xive->tctxt_regs[reg] = val;
          break;
      default:
-        xive2_error(xive, "TCTXT: invalid write @%"HWADDR_PRIx, offset);
+        xive2_error(xive, "TCTXT: invalid write @0x%"HWADDR_PRIx
+                    " data 0x%"PRIx64, offset, val);
          return;
      }
  }
@@ -1861,7 +1865,8 @@ static void pnv_xive2_xscom_write(void *opaque, hwaddr 
offset,
          pnv_xive2_ic_tctxt_write(opaque, mmio_offset, val, size);
          break;
      default:
-        xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx, offset);
+        xive2_error(xive, "XSCOM: invalid write @%"HWADDR_PRIx
+                    " value 0x%"PRIx64, offset, val);
      }
  }

@@ -1929,7 +1934,8 @@ static void pnv_xive2_ic_notify_write(void *opaque, hwaddr offset,

          break;

default:

-        xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx, offset);
+        xive2_error(xive, "NOTIFY: invalid write @%"HWADDR_PRIx
+                    " value 0x%"PRIx64, offset, val);
      }
  }

@@ -1971,7 +1977,8 @@ static void pnv_xive2_ic_lsi_write(void *opaque, hwaddr offset,

  {
      PnvXive2 *xive = PNV_XIVE2(opaque);

- xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx, offset);

+    xive2_error(xive, "LSI: invalid write @%"HWADDR_PRIx" value 0x%"PRIx64,
+                offset, val);
  }

static const MemoryRegionOps pnv_xive2_ic_lsi_ops = {

@@ -2074,7 +2081,8 @@ static void pnv_xive2_ic_sync_write(void *opaque, hwaddr 
offset,
          inject_type = PNV_XIVE2_QUEUE_NXC_ST_RMT_CI;
          break;
      default:
-        xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx, offset);
+        xive2_error(xive, "SYNC: invalid write @%"HWADDR_PRIx" value 
0x%"PRIx64,
+                    offset, val);
          return;
      }